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Commit 1ed6c0ee authored by David Cussans's avatar David Cussans
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Sorting out scripts

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components/tlu/firmware/hdl/IPBusInterface_rtl.vhd deleted 100644 → 0
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--=============================================================================
--! @file IPBusInterface_rtl.vhd
--=============================================================================
--
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- VHDL Architecture fmc_mTLU_lib.IPBusInterface.rtl
--
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.ipbus.all;
--! @brief IPBus interface between 1GBit/s Ethernet and IPBus internal bus
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date 16:06:57 11/09/12
--
--! @version v0.1
--
--! @details
--!
--! <b>Modified by:</b>\n
--! Author:
-------------------------------------------------------------------------------
--! \n\n<b>Last changes:</b>\n
-------------------------------------------------------------------------------
ENTITY IPBusInterface IS
GENERIC(
NUM_EXT_SLAVES : positive := 5;
BUILD_SIMULATED_ETHERNET : integer := 0 --! Set to 1 to build simulated Ethernet interface using Modelsim FLI
);
PORT(
gmii_rx_clk_i : IN std_logic;
gmii_rx_dv_i : IN std_logic;
gmii_rx_er_i : IN std_logic;
gmii_rxd_i : IN std_logic_vector (7 DOWNTO 0);
ipbr_i : IN ipb_rbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); --! IPBus read signals
sysclk_n_i : IN std_logic;
sysclk_p_i : IN std_logic; --! 200 MHz xtal clock
clocks_locked_o : OUT std_logic;
gmii_gtx_clk_o : OUT std_logic;
gmii_tx_en_o : OUT std_logic;
gmii_tx_er_o : OUT std_logic;
gmii_txd_o : OUT std_logic_vector (7 DOWNTO 0);
ipb_clk_o : OUT std_logic; --! IPBus clock to slaves
ipb_rst_o : OUT std_logic; --! IPBus reset to slaves
ipbw_o : OUT ipb_wbus_array (NUM_EXT_SLAVES-1 DOWNTO 0); --! IBus write signals
onehz_o : OUT std_logic;
phy_rstb_o : OUT std_logic;
dip_switch_i : IN std_logic_vector (3 DOWNTO 0); --! Used to select IP address
clk_logic_xtal_o : OUT std_logic --! 40MHz clock that can be used for logic if not using external clock
);
-- Declarations
END ENTITY IPBusInterface ;
--
ARCHITECTURE rtl OF IPBusInterface IS
--! Number of slaves inside the IPBusInterface block.
constant c_NUM_INTERNAL_SLAVES : positive := 1;
signal clk125, rst_125, rst_ipb: STD_LOGIC;
signal mac_txd, mac_rxd : STD_LOGIC_VECTOR(7 downto 0);
signal mac_txdvld, mac_txack, mac_rxclko, mac_rxdvld, mac_rxgoodframe, mac_rxbadframe : STD_LOGIC;
signal ipb_master_out : ipb_wbus;
signal ipb_master_in : ipb_rbus;
signal mac_addr: std_logic_vector(47 downto 0);
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal ip_addr: std_logic_vector(31 downto 0);
signal s_ipb_clk : std_logic;
signal s_ipbw_internal: ipb_wbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_ipbr_internal: ipb_rbus_array (NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1 DOWNTO 0);
signal s_sysclk : std_logic;
signal pkt_rx, pkt_tx, pkt_rx_led, pkt_tx_led, sys_rst: std_logic;
BEGIN
-- Connect IPBus clock and reset to output ports.
ipb_clk_o <= s_ipb_clk;
ipb_rst_o <= rst_ipb;
--! By default generate a physical MAC
generate_physicalmac: if ( BUILD_SIMULATED_ETHERNET /= 1 ) generate
-- DCM clock generation for internal bus, ethernet
-- clocks: entity work.clocks_s6_extphy port map(
-- sysclk_p => sysclk_p_i,
-- sysclk_n => sysclk_n_i,
-- clk_logic_xtal_o => clk_logic_xtal_o,
-- clko_125 => clk125,
-- clko_ipb => s_ipb_clk,
-- locked => clocks_locked_o,
-- rsto_125 => rst_125,
-- rsto_ipb => rst_ipb,
-- onehz => onehz_o
-- );
clocks: entity work.clocks_7s_extphy_Se port map(
sysclk_p => sysclk_p_i,
sysclk_n => sysclk_n_i,
clk_logic_xtal_o => clk_logic_xtal_o,
clko_125 => clk125,
clko_ipb => s_ipb_clk,
locked => clocks_locked_o,
rsto_125 => rst_125,
rsto_ipb => rst_ipb,
onehz => onehz_o
);
-- leds <= ('0', '0', locked, onehz);
-- Ethernet MAC core and PHY interface
-- In this version, consists of hard MAC core and GMII interface to external PHY
-- Can be replaced by any other MAC / PHY combination
-- eth: entity work.eth_s6_gmii port map(
-- clk125 => clk125,
-- rst => rst_125,
-- gmii_gtx_clk => gmii_gtx_clk_o,
-- gmii_tx_en => gmii_tx_en_o,
-- gmii_tx_er => gmii_tx_er_o,
-- gmii_txd => gmii_txd_o,
-- gmii_rx_clk => gmii_rx_clk_i,
-- gmii_rx_dv => gmii_rx_dv_i,
-- gmii_rx_er => gmii_rx_er_i,
-- gmii_rxd => gmii_rxd_i,
-- tx_data => mac_tx_data,
-- tx_valid => mac_tx_valid,
-- tx_last => mac_tx_last,
-- tx_error => mac_tx_error,
-- tx_ready => mac_tx_ready,
-- rx_data => mac_rx_data,
-- rx_valid => mac_rx_valid,
-- rx_last => mac_rx_last,
-- rx_error => mac_rx_error
-- );
eth: entity work.eth_7s_rgmii port map(
clk125 => clk125,
rst => rst_125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error,
gmii_gtx_clk => gmii_gtx_clk_o,
gmii_tx_en => gmii_tx_en_o,
gmii_tx_er => gmii_tx_er_o,
gmii_txd => gmii_txd_o,
gmii_rx_clk => gmii_rx_clk_i,
gmii_rx_dv => gmii_rx_dv_i,
gmii_rx_er => gmii_rx_er_i,
gmii_rxd => gmii_rxd_i
);
end generate generate_physicalmac;
--! Set generic BUILD_SIMULATED_ETHERNET to 1 to generate a simulated MAC
generate_simulatedmac: if ( BUILD_SIMULATED_ETHERNET = 1 ) generate
sim_clocks: entity work.clock_sim
port map (
clko125 => clk125,
clko25 => s_ipb_clk,
clko40 => clk_logic_xtal_o,
nuke => '0',
rsto => rst_125
);
rst_ipb <= rst_125;
clocks_locked_o <= '1';
-- clk125 <= sysclk_i; -- *must* run this simulation with 125MHz sysclk...
simulated_eth: entity work.eth_mac_sim
port map(
clk => clk125,
rst => rst_125,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
end generate generate_simulatedmac;
phy_rstb_o <= '1';
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
generic map (
BUFWIDTH => 2)
port map(
mac_clk => clk125,
rst_macclk => rst_125,
ipb_clk => s_ipb_clk,
rst_ipb => rst_ipb,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_master_out,
ipb_in => ipb_master_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt_rx => pkt_rx,
pkt_tx => pkt_tx,
pkt_rx_led => pkt_rx_led,
pkt_tx_led => pkt_tx_led
);
mac_addr <= X"020ddba115" & dip_switch_i & X"0"; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c8" & dip_switch_i & X"0"; -- 192.168.200.X
fabric: entity work.ipbus_fabric
generic map(NSLV => NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES)
port map(
ipb_in => ipb_master_out,
ipb_out => ipb_master_in,
ipb_to_slaves => s_ipbw_internal,
ipb_from_slaves => s_ipbr_internal
);
ipbw_o <= s_ipbw_internal(NUM_EXT_SLAVES-1 downto 0);
s_ipbr_internal(NUM_EXT_SLAVES-1 downto 0) <= ipbr_i;
-- Slave: firmware ID
firmware_id: entity work.ipbus_ver
port map(
ipbus_in => s_ipbw_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1),
ipbus_out => s_ipbr_internal(NUM_EXT_SLAVES+c_NUM_INTERNAL_SLAVES-1)
);
END ARCHITECTURE rtl;
components/tlu/firmware/hdl/ipbus_ver.vhd deleted 100644 → 0
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--=============================================================================
--! @file ipbus_ver.vhd
--=============================================================================
-- Version register, returns a fixed value
--
-- To be replaced by a more coherent versioning mechanism later
--
-- Dave Newbold, August 2011
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
--! @brief IPBus fixed register returning Firmware version number
entity ipbus_ver is
port(
ipbus_in: in ipb_wbus;
ipbus_out: out ipb_rbus
);
end ipbus_ver;
architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a622" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
end rtl;
-- Build log
--
-- build 0x1000 : 22/08/11 : Starting build ID
-- build 0x1001 : 29/08/11 : Version for SPI testing
-- build 0x1002 : 27/09/11 : Bug fixes, new transactor code; v1.3 candidate
-- build 0x1003 : buggy
-- build 0x1004 : 18/10/11 : New mini-t top level, bug fixes, 1.3 codebase
-- build 0x1005 : 20/10/11 : ipbus address config testing in mini-t
-- build 0x1006 : 26/10/11 : trying with jumbo frames
-- build 0x1007 : 27/10/11 : new slaves / address map + rhino frames
-- build 0x1008 : 31/10/11 : rhino frames + multibus demo
projects/TLU_v1e/addr_table/TLUaddrmap.xml
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......@@ -17,13 +17,13 @@
</node>
<node id="Shutter" address="0x2000" description="Shutter/T0 control" fwinfo="endpoint;width=4">
<node id="ControlW" address="0x0" permission="w" description="Bit-0 controls if shutter pulses are active. 1 = active"/>
<node id="ShutterSelectW" address="0x1" permission="w" description="Selects which input is used to trigger shutter"/>
<node id="InternalShutterPeriodW" address="0x2" permission="w" description="Internal trig generator period ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x3" permission="w" description="Time between input trigger being received and shutter asserted(T1) ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x4" permission="w" description="time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x5" permission="w" description="time at which shutter de-asserted(T3) ( units = number of strobe pulses)"/>
<node id="PulseT0" address="0x8" permission="w" description="Writing to Bit-0 of this register causes sync line to pulse for one strobe-pulse interval"/>
<node id="ControlW" address="0x0" permission="rw" description="Bit-0 controls if shutter pulses are active. 1 = active"/>
<node id="ShutterSelectW" address="0x1" permission="rw" description="Selects which input is used to trigger shutter"/>
<node id="InternalShutterPeriodW" address="0x2" permission="rw" description="Internal trig generator period ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x3" permission="rw" description="Time between input trigger being received and shutter asserted(T1) ( units = number of strobe pulses)"/>
<node id="VetoOffTimeW" address="0x4" permission="rw" description="time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)"/>
<node id="ShutterOffTimeW" address="0x5" permission="rw" description="time between input trigger and time at which shutter de-asserted and veto reasserted(T3) ( units = number of strobe pulses)"/>
<node id="PulseT0" address="0x8" permission="rw" description="Writing to Bit-0 of this register causes sync line to pulse for one strobe-pulse interval"/>
</node>
<!-- I2C registers. Tested ok.-->
<node id="i2c_master" address="0x3000" description="I2C Master interface" fwinfo="endpoint;width=3">
......
projects/TLU_v1e/scripts/AD5665R.py 0 → 120000
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packages/AD5665R.py
\ No newline at end of file
projects/TLU_v1e/scripts/AIDA_testScript.py 0 → 100644
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# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "CHECK REG= ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
# #######################################
#
# time.sleep(0.1)
# #Read the EPROM
# mystop=False
# nwords=6
# myslave= 0x53 #DUNE EPROM 0x53 (Possibly)
# myaddr= [0xfa]#0xfa
# master_I2C.write( myslave, myaddr, mystop)
# #res= master_I2C.read( 0x50, 6)
# res= master_I2C.read( myslave, nwords)
# print " PCB EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
# #######################################
#Second I2C core
#print ("Instantiating SFP I2C core:")
#clock_I2C= I2CCore(hw, 10, 5, "i2c_sfp", None)
#clock_I2C.state()
# #Third I2C core
# print ("Instantiating clock I2C core:")
# clock_I2C= I2CCore(hw, 10, 5, "i2c_clk", None)
# clock_I2C.state()
# #time.sleep(0.01)
# #Read the EPROM
# mystop=False
# nwords=2
# myslave= 0x68 #DUNE CLOCK CHIP 0x68
# myaddr= [0x02 ]#0xfa
# clock_I2C.write( myslave, myaddr, mystop)
# #time.sleep(0.1)
# res= clock_I2C.read( myslave, nwords)
# print " CLOCK EPROM: "
# result="\t "
# for iaddr in res:
# result+="%02x "%(iaddr)
# print result
#
#CLOCK CONFIGURATION BEGIN
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
#clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
clkRegList= zeClock.parse_clk("./localClock.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL (0x000E): 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS (0x000D): 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(0, 0xFF)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(1, 0xFF)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0xFF)# 0= normal
IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(0, 0xFF)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x4F)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# #Reset counters
#cmd = int("0x0", 16) #write 0x2 to reset
#hw.getNode("triggerInputs.SerdesRstW").write(cmd)
#restatus= hw.getNode("triggerInputs.SerdesRstR").read()
#hw.dispatch()
#print "Trigger Reset: 0x%X" % restatus
## #Read trigger inputs
#myreg= [-1, -1, -1, -1, -1, -1]
#for inputN in range(0, 6):
# regString= "triggerInputs.ThrCount%dR" % inputN
# myreg[inputN]= hw.getNode(regString).read()
# hw.dispatch()
# print regString, myreg[inputN]
## Read ev formatter
#cmd = int("0x0", 16) #
##hw.getNode("Event_Formatter.Enable_Record_Data").write(cmd)
#efstatus= hw.getNode("Event_Formatter.CurrentTimestampLR").read()
#hw.dispatch()
#print "Event Formatter Record: 0x%X" % efstatus
projects/TLU_v1e/scripts/AIDA_testShutter.py 0 → 100644
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# -*- coding: utf-8 -*-
#
# Sets up AIDA-2020 TLU to produce shutter signals.
# After running this script there should be shutter signals on all DUT interfaces
#
import uhal
from I2CuHal import I2CCore
import time
#import miniTLU
from si5345 import si5345
from AD5665R import AD5665R
from PCA9539PW import PCA9539PW
from E24AA025E48T import E24AA025E48T
manager = uhal.ConnectionManager("file://./TLUconnection.xml")
hw = manager.getDevice("tlu")
# hw.getNode("A").write(255)
reg = hw.getNode("version").read()
hw.dispatch()
print "Firmware Version Number = ", hex(reg)
# #First I2C core
print ("Instantiating master I2C core:")
master_I2C= I2CCore(hw, 10, 5, "i2c_master", None)
master_I2C.state()
#
# #######################################
enableCore= True #Only need to run this once, after power-up
if (enableCore):
mystop=True
print " Write RegDir to set I/O[7] to output:"
myslave= 0x21
mycmd= [0x01, 0x7F]
nwords= 1
master_I2C.write(myslave, mycmd, mystop)
mystop=False
mycmd= [0x01]
master_I2C.write(myslave, mycmd, mystop)
res= master_I2C.read( myslave, nwords)
print "\tPost RegDir: ", res
#CLOCK CONFIGURATION BEGIN
print "Setting up clock"
zeClock=si5345(master_I2C, 0x68)
res= zeClock.getDeviceVersion()
zeClock.checkDesignID()
#zeClock.setPage(0, True)
#zeClock.getPage(True)
#clkRegList= zeClock.parse_clk("./../../bitFiles/TLU_CLK_Config_v1e.txt")
clkRegList= zeClock.parse_clk("./localClock.txt")
zeClock.writeConfiguration(clkRegList)######
zeClock.writeRegister(0x0536, [0x0A]) #Configures manual switch of inputs
zeClock.writeRegister(0x0949, [0x0F]) #Enable all inputs
zeClock.writeRegister(0x052A, [0x05]) #Configures source of input
iopower= zeClock.readRegister(0x0949, 1)
print " Clock IO power: 0x%X" % iopower[0]
lol= zeClock.readRegister(0x000E, 1)
print " Clock LOL (0x000E): 0x%X" % lol[0]
los= zeClock.readRegister(0x000D, 1)
print " Clock LOS (0x000D): 0x%X" % los[0]
#CLOCK CONFIGURATION END
#DAC CONFIGURATION BEGIN
zeDAC1=AD5665R(master_I2C, 0x13)
zeDAC1.setIntRef(intRef= False, verbose= True)
zeDAC1.writeDAC(0x0, 7, verbose= True)#7626
zeDAC2=AD5665R(master_I2C, 0x1F)
zeDAC2.setIntRef(intRef= False, verbose= True)
zeDAC2.writeDAC(0x2fff, 3, verbose= True)
#DAC CONFIGURATION END
#EEPROM BEGIN
zeEEPROM= E24AA025E48T(master_I2C, 0x50)
res=zeEEPROM.readEEPROM(0xfa, 6)
result=" EEPROM ID:\n\t"
for iaddr in res:
result+="%02x "%(iaddr)
print result
#EEPROM END
# #I2C EXPANDER CONFIGURATION BEGIN
IC6=PCA9539PW(master_I2C, 0x74)
#BANK 0
IC6.setInvertReg(0, 0x00)# 0= normal
IC6.setIOReg(0, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(0, 0xFF)
res= IC6.getInputs(0)
print "IC6 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC6.setInvertReg(1, 0x00)# 0= normal
IC6.setIOReg(1, 0xFF)# 0= output <<<<<<<<<<<<<<<<<<<
IC6.setOutputs(1, 0xFF)
res= IC6.getInputs(1)
print "IC6 read back bank 1: 0x%X" % res[0]
# # #
IC7=PCA9539PW(master_I2C, 0x75)
#BANK 0
IC7.setInvertReg(0, 0xFF)# 0= normal
IC7.setIOReg(0, 0xFA)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(0, 0xFF)
res= IC7.getInputs(0)
print "IC7 read back bank 0: 0x%X" % res[0]
#
#BANK 1
IC7.setInvertReg(1, 0x00)# 0= normal
IC7.setIOReg(1, 0x4F)# 0= output <<<<<<<<<<<<<<<<<<<
IC7.setOutputs(1, 0xFF)
res= IC7.getInputs(1)
print "IC7 read back bank 1: 0x%X" % res[0]
# #I2C EXPANDER CONFIGURATION END
# Set up shutter registers
print "Setting up shutter registers"
shutterPeriod = 1024
T1 = 100
T2 = 200
T3 = 300
hw.getNode("Shutter.InternalShutterPeriodW").write(shutterPeriod)
hw.getNode("Shutter.ShutterOnTimeW").write(T1)
hw.getNode("Shutter.VetoOffTimeW").write(T2)
hw.getNode("Shutter.ShutterOffTimeW").write(T3)
# Enable shutter signal and internal sequence generator
hw.getNode("Shutter.ControlW").write(2)
# Enable DUT intefaces
hw.getNode("DUTInterfaces.DutMaskW").write(0xF)
hw.getNode("DUTInterfaces.IgnoreDUTBusyW").write(0xF)
hw.dispatch()
print "All done"
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packages/E24AA025E48T.py
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./packages/I2CuHal.py
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packages/PCA9539PW.py
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projects/TLU_v1e/scripts/TLU_v1e.py 0 → 100644
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../addr_table/TLUaddrmap.xml
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<?xml version="1.0" encoding="ISO-8859-1"?>
<node id="TLU">
<!-- Registers for the DUTs. These should be correct -->
<node id="DUTInterfaces" address="0x1000" description="DUT Interfaces control registers">
<node id="DutMaskW" address="0x0" permission="w" description="" />
<node id="IgnoreDUTBusyW" address="0x1" permission="w" description="" />
<node id="IgnoreShutterVetoW" address="0x2" permission="w" description="" />
<node id="DUTInterfaceModeW" address="0x3" permission="w" description="" />
<node id="DUTInterfaceModeModifierW" address="0x4" permission="w" description="" />
<node id="DUTInterfaceModeR" address="0xB" permission="r" description="" />
<node id="DUTInterfaceModeModifierR" address="0xC" permission="r" description="" />
<node id="DutMaskR" address="0x8" permission="r" description="" />
<node id="IgnoreDUTBusyR" address="0x9" permission="r" description="" />
<node id="IgnoreShutterVetoR" address="0xA" permission="r" description="" />
</node>
<node id="Shutter" address="0x2000" description="Shutter/T0 control">
<node id="ShutterStateW" address="0x0" permission="w" description=""/>
<node id="PulseT0" address="0x1" permission="w" description=""/>
</node>
<!-- I2C registers. Tested ok.-->
<node id="i2c_master" address="0x3000" description="I2C Master interface">
<node id="i2c_pre_lo" address="0x0" mask="0x000000ff" permission="rw" description="" />
<node id="i2c_pre_hi" address="0x1" mask="0x000000ff" permission="rw" description="" />
<node id="i2c_ctrl" address="0x2" mask="0x000000ff" permission="rw" description="" />
<node id="i2c_rxtx" address="0x3" mask="0x000000ff" permission="rw" description="" />
<node id="i2c_cmdstatus" address="0x4" mask="0x000000ff" permission="rw" description="" />
</node>
<!-- Not sure about the FillLevelFlags register -->
<node id="eventBuffer" address="0x4000" description="Event buffer">
<node id="EventFifoData" address="0x0" mode="non-incremental" size="32000" permission="r" description="" />
<node id="EventFifoFillLevel" address="0x1" permission="r" description="" />
<node id="EventFifoCSR" address="0x2" permission="rw" description="" />
<node id="EventFifoFillLevelFlags" address="0x3" permission="r" description="" />
</node>
<!-- Event formatter registers. Should be ok -->
<node id="Event_Formatter" address="0x5000" description="Event formatter configuration">
<node id="Enable_Record_Data" address="0x0" permission="rw" description="" />
<node id="ResetTimestampW" address="0x1" permission="w" description="" />
<node id="CurrentTimestampLR" address="0x2" permission="r" description="" />
<node id="CurrentTimestampHR" address="0x3" permission="r" description="" />
</node>
<!-- This needs checking. The counters work, not sure about the reset -->
<node id="triggerInputs" address="0x6000" description="Inputs configuration">
<node id="SerdesRstW" address="0x0" permission="w" description="" />
<node id="SerdesRstR" address="0x8" permission="r" description="" />
<node id="ThrCount0R" address="0x9" permission="r" description="" />
<node id="ThrCount1R" address="0xa" permission="r" description="" />
<node id="ThrCount2R" address="0xb" permission="r" description="" />
<node id="ThrCount3R" address="0xc" permission="r" description="" />
<node id="ThrCount4R" address="0xd" permission="r" description="" />
<node id="ThrCount5R" address="0xe" permission="r" description="" />
</node>
<!-- Checked. Seems ok now, except for the TriggerVeto that do nothing.-->
<node id="triggerLogic" address="0x7000" description="Trigger logic configuration">
<node id="PostVetoTriggersR" address="0x10" permission="r" description="" />
<node id="PreVetoTriggersR" address="0x11" permission="r" description="" />
<node id="InternalTriggerIntervalW" address="0x2" permission="w" description="" />
<node id="InternalTriggerIntervalR" address="0x12" permission="r" description="" />
<!--<node id="TriggerPatternW" address="0x3" permission="w" description="" />-->
<!--<node id="TriggerPatternR" address="0x13" permission="r" description="" />-->
<node id="TriggerVetoW" address="0x4" permission="w" description="" />
<node id="TriggerVetoR" address="0x14" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
<node id="ExternalTriggerVetoR" address="0x15" permission="r" description="" />
<node id="PulseStretchW" address="0x6" permission="w" description="" />
<node id="PulseStretchR" address="0x16" permission="r" description="" />
<node id="PulseDelayW" address="0x7" permission="w" description="" />
<node id="PulseDelayR" address="0x17" permission="r" description="" />
<node id="TriggerHoldOffW" address="0x8" permission="W" description="" /><!--Wait, this does nothing at the moment...-->
<node id="TriggerHoldOffR" address="0x18" permission="r" description="" /><!--Wait, this does nothing at the moment...-->
<node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
<node id="TriggerPattern_lowW" address="0xA" permission="w" description="" />
<node id="TriggerPattern_lowR" address="0x1A" permission="r" description="" />
<node id="TriggerPattern_highW" address="0xB" permission="w" description="" />
<node id="TriggerPattern_highR" address="0x1B" permission="r" description="" />
<!--<node id="PulseStretchW" address="0x6" permission="w" description="" /> OLD REGISTER MAP. WAS BUGGED-->
<!--<node id="PulseStretchR" address="0x16" permission="r" description="" /> OLD REGISTER MAP. WAS BUGGED-->
<!--
<node id="ResetCountersW" address="0x6" permission="w" description="" />
<node id="PulseStretchR" address="0x17" permission="r" description="" />
<node id="PulseStretchW" address="0x7" permission="w" description="" />
<node id="TriggerHoldOffR" address="0x18" permission="r" description="" />
<node id="TriggerHoldOffW" address="0x8" permission="W" description="" />
<node id="AuxTriggerCountR" address="0x19" permission="r" description="" />
-->
</node>
<node id="logic_clocks" address="0x8000" description="Clocks configuration">
<node id="LogicClocksCSR" address="0x0" permission="rw" description="" />
<node id="LogicRst" address="0x1" permission="w" description="" />
</node>
<node id="version" address="0x1" description="firmware version" permission="r">
</node>
<!--
PulseStretchW 0x00000066 0xffffffff 0 1
PulseDelayW 0x00000067 0xffffffff 0 1
PulseDelayR 0x00000077 0xffffffff 1 0
-->
</node>
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<?xml version="1.0" encoding="UTF-8"?>
<connections>
<connection id="tlu" uri="ipbusudp-2.0://192.168.200.30:50001"
address_table="file://./TLUaddrmap.xml" />
</connections>
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#
# Function to initialize TLU
#
# David Cussans, October 2015
#
# Nasty hack - use both PyChips and uHAL ( for block read ... )
from PyChipsUser import *
from FmcTluI2c import *
import uhal
import sys
import time
def startTLU( uhalDevice , pychipsBoard , writeTimestamps):
print "RESETTING FIFO"
pychipsBoard.write("EventFifoCSR",0x2)
eventFifoFillLevel = pychipsBoard.read("EventFifoFillLevel")
print "FIFO FILL LEVEL AFTER RESET= " , eventFifoFillLevel
if writeTimestamps:
print "ENABLING DATA RECORDING"
pychipsBoard.write("Enable_Record_Data",1)
else:
print "Disabling data recording"
pychipsBoard.write("Enable_Record_Data",0)
print "Pulsing T0"
pychipsBoard.write("PulseT0",1)
print "Turning off software trigger veto"
pychipsBoard.write("TriggerVetoW",0)
print "TLU is running"
def stopTLU( uhalDevice , pychipsBoard ):
print "Turning on software trigger veto"
pychipsBoard.write("TriggerVetoW",1)
print "TLU triggers are stopped"
def initTLU( uhalDevice , pychipsBoard , listenForTelescopeShutter , pulseDelay , pulseStretch , triggerPattern , DUTMask , ignoreDUTBusy , triggerInterval , thresholdVoltage ):
print "SETTING UP AIDA TLU"
fwVersion = uhalDevice.getNode("version").read()
uhalDevice.dispatch()
print "\tVersion (uHAL)= " , hex(fwVersion)
print "\tTurning on software trigger veto"
pychipsBoard.write("TriggerVetoW",1)
# Check the bus for I2C devices
pychipsBoardi2c = FmcTluI2c(pychipsBoard)
print "\tScanning I2C bus:"
scanResults = pychipsBoardi2c.i2c_scan()
#print scanResults
print '\t', ', '.join(scanResults), '\n'
boardId = pychipsBoardi2c.get_serial_number()
print "\tFMC-TLU serial number= " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "\tSETTING ALL DAC THRESHOLDS TO" , thresholdVoltage , "V"
pychipsBoardi2c.set_threshold_voltage(7, thresholdVoltage)
clockStatus = pychipsBoard.read("LogicClocksCSR")
print "\tCLOCK STATUS (should be 3 if all clocks locked)= " , hex(clockStatus)
assert ( clockStatus == 3 ) , "Clocks in TLU FPGA are not locked. No point in continuing. Re-prgramme or power cycle board"
if resetClocks:
print "Resetting clocks"
pychipsBoard.write("LogicRst", 1 )
clockStatus = pychipsBoard.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
pychipsBoard.write("SerdesRstW", 0x00000003 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
pychipsBoard.write("SerdesRstW", 0x00000000 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
pychipsBoard.write("SerdesRstW", 0x00000004 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
pychipsBoard.write("SerdesRstW", 0x00000000 )
inputStatus = pychipsBoard.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
inputStatus = pychipsBoard.read("SerdesRstR")
print "\tINPUT STATUS= " , hex(inputStatus)
count0 = pychipsBoard.read("ThrCount0R")
print "\t Count 0= " , count0
count1 = pychipsBoard.read("ThrCount1R")
print "\t Count 1= " , count1
count2 = pychipsBoard.read("ThrCount2R")
print "\t Count 2= " , count2
count3 = pychipsBoard.read("ThrCount3R")
print "\t Count 3= " , count3
# Stop internal triggers until setup complete
pychipsBoard.write("InternalTriggerIntervalW",0)
print "\tSETTING INPUT COINCIDENCE WINDOW TO",pulseStretch,"[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
pychipsBoard.write("PulseStretchW",int(pulseStretch))
pulseStretchR = pychipsBoard.read("PulseStretchR")
print "\t Pulse stretch read back as:", hex(pulseStretchR)
# assert (int(pulseStretch) == pulseStretchR) , "Pulse stretch read-back doesn't equal written value"
print "\tSETTING INPUT TRIGGER DELAY TO",pulseDelay , "[Units= 160MHz clock cycles, Four 5-bit values (one per input) packed in to 32-bit word]"
pychipsBoard.write("PulseDelayW",int(pulseDelay))
pulseDelayR = pychipsBoard.read("PulseDelayR")
print "\t Pulse delay read back as:", hex(pulseDelayR)
print "\tSETTING TRIGGER PATTERN (for external triggers) TO 0x%08X. Two 16-bit patterns packed into 32 bit word " %(triggerPattern)
pychipsBoard.write("TriggerPatternW",int(triggerPattern))
triggerPatternR = pychipsBoard.read("TriggerPatternR")
print "\t Trigger pattern read back as: 0x%08X " % (triggerPatternR)
print "\tENABLING DUT(s): Mask= " , hex(DUTMask)
pychipsBoard.write("DUTMaskW",int(DUTMask))
DUTMaskR = pychipsBoard.read("DUTMaskR")
print "\t DUTMask read back as:" , hex(DUTMaskR)
print "\tSETTING ALL DUTs IN AIDA MODE"
pychipsBoard.write("DUTInterfaceModeW", 0xFF)
DUTInterfaceModeR = pychipsBoard.read("DUTInterfaceModeR")
print "\t DUT mode read back as:" , DUTInterfaceModeR
print "\tSET DUT MODE MODIFIER"
pychipsBoard.write("DUTInterfaceModeModifierW", 0xFF)
DUTInterfaceModeModifierR = pychipsBoard.read("DUTInterfaceModeModifierR")
print "\t DUT mode modifier read back as:" , DUTInterfaceModeModifierR
if listenForTelescopeShutter:
print "\tSET IgnoreShutterVetoW TO LISTEN FOR VETO FROM SHUTTER"
pychipsBoard.write("IgnoreShutterVetoW",0)
else:
print "\tSET IgnoreShutterVetoW TO IGNORE VETO FROM SHUTTER"
pychipsBoard.write("IgnoreShutterVetoW",1)
IgnoreShutterVeto = pychipsBoard.read("IgnoreShutterVetoR")
print "\t IgnoreShutterVeto read back as:" , IgnoreShutterVeto
print "\tSETTING IGNORE VETO BY DUT BUSY MASK TO" , hex(ignoreDUTBusy)
pychipsBoard.write("IgnoreDUTBusyW",int(ignoreDUTBusy))
IgnoreDUTBusy = pychipsBoard.read("IgnoreDUTBusyR")
print "\t IgnoreDUTBusy read back as:" , hex(IgnoreDUTBusy)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
print "\tSETTING INTERNAL TRIGGER INTERVAL TO" , triggerInterval , "(zero= no internal triggers)"
if triggerInterval == 0:
internalTriggerFreq = 0
else:
internalTriggerFreq = 160000.0/triggerInterval
print "\tINTERNAL TRIGGER FREQUENCY= " , internalTriggerFreq , " kHz"
pychipsBoard.write("InternalTriggerIntervalW",triggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigIntervalR = pychipsBoard.read("InternalTriggerIntervalR")
print "\t Trigger interval read back as:", trigIntervalR
print "AIDA TLU SETUP COMPLETED"
projects/TLU_v1e/scripts/localClock.txt 0 → 100644
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# Si538x/4x Registers Export
#
# Part: Si5345
# Project File: P:\cad\designs\fmc-mtlu\trunk\circuit_board\Cadence\worklib\fmc_tlu_toplevel_c\physical\ClockGen\TLU_Si5345-RevB-NEWTLU00-Project.slabtimeproj
# Design ID: TLU1E_01
# Includes Pre/Post Download Control Register Writes: Yes
# Die Revision: A2
# Creator: ClockBuilder Pro v2.12.1 [2016-12-15]
# Created On: 2017-08-24 13:37:41 GMT+01:00
Address,Data
0x0B24,0xD8
0x0B25,0x00
0x000B,0x68
0x0016,0x02
0x0017,0x1C
0x0018,0x88
0x0019,0xDD
0x001A,0xDF
0x002B,0x02
0x002C,0x07
0x002D,0x15
0x002E,0x37
0x002F,0x00
0x0030,0x37
0x0031,0x00
0x0032,0x37
0x0033,0x00
0x0034,0x00
0x0035,0x00
0x0036,0x37
0x0037,0x00
0x0038,0x37
0x0039,0x00
0x003A,0x37
0x003B,0x00
0x003C,0x00
0x003D,0x00
0x003F,0x77
0x0040,0x04
0x0041,0x0C
0x0042,0x0C
0x0043,0x0C
0x0044,0x00
0x0045,0x0C
0x0046,0x32
0x0047,0x32
0x0048,0x32
0x0049,0x00
0x004A,0x32
0x004B,0x32
0x004C,0x32
0x004D,0x00
0x004E,0x55
0x004F,0x05
0x0051,0x03
0x0052,0x03
0x0053,0x03
0x0054,0x00
0x0055,0x03
0x0056,0x03
0x0057,0x03
0x0058,0x00
0x0059,0x3F
0x005A,0xCC
0x005B,0xCC
0x005C,0xCC
0x005D,0x00
0x005E,0xCC
0x005F,0xCC
0x0060,0xCC
0x0061,0x00
0x0062,0xCC
0x0063,0xCC
0x0064,0xCC
0x0065,0x00
0x0066,0x00
0x0067,0x00
0x0068,0x00
0x0069,0x00
0x0092,0x00
0x0093,0x00
0x0095,0x00
0x0096,0x00
0x0098,0x00
0x009A,0x02
0x009B,0x30
0x009D,0x00
0x009E,0x20
0x00A0,0x00
0x00A2,0x02
0x00A8,0x89
0x00A9,0x70
0x00AA,0x07
0x00AB,0x00
0x00AC,0x00
0x0102,0x01
0x0108,0x06
0x0109,0x09
0x010A,0x33
0x010B,0x00
0x010D,0x06
0x010E,0x09
0x010F,0x33
0x0110,0x00
0x0112,0x06
0x0113,0x09
0x0114,0x33
0x0115,0x00
0x0117,0x06
0x0118,0x09
0x0119,0x33
0x011A,0x00
0x011C,0x06
0x011D,0x09
0x011E,0x33
0x011F,0x00
0x0121,0x06
0x0122,0x09
0x0123,0x33
0x0124,0x00
0x0126,0x06
0x0127,0x09
0x0128,0x33
0x0129,0x00
0x012B,0x06
0x012C,0x09
0x012D,0x33
0x012E,0x00
0x0130,0x06
0x0131,0x09
0x0132,0x33
0x0133,0x00
0x013A,0x01
0x013B,0xCC
0x013C,0x00
0x013D,0x00
0x013F,0x00
0x0140,0x00
0x0141,0x40
0x0142,0xFF
0x0202,0x00
0x0203,0x00
0x0204,0x00
0x0205,0x00
0x0206,0x00
0x0208,0x14
0x0209,0x00
0x020A,0x00
0x020B,0x00
0x020C,0x00
0x020D,0x00
0x020E,0x01
0x020F,0x00
0x0210,0x00
0x0211,0x00
0x0212,0x14
0x0213,0x00
0x0214,0x00
0x0215,0x00
0x0216,0x00
0x0217,0x00
0x0218,0x01
0x0219,0x00
0x021A,0x00
0x021B,0x00
0x021C,0x14
0x021D,0x00
0x021E,0x00
0x021F,0x00
0x0220,0x00
0x0221,0x00
0x0222,0x01
0x0223,0x00
0x0224,0x00
0x0225,0x00
0x0226,0x00
0x0227,0x00
0x0228,0x00
0x0229,0x00
0x022A,0x00
0x022B,0x00
0x022C,0x00
0x022D,0x00
0x022E,0x00
0x022F,0x00
0x0231,0x01
0x0232,0x01
0x0233,0x01
0x0234,0x01
0x0235,0x00
0x0236,0x00
0x0237,0x00
0x0238,0x00
0x0239,0xA9
0x023A,0x00
0x023B,0x00
0x023C,0x00
0x023D,0x00
0x023E,0xA0
0x024A,0x00
0x024B,0x00
0x024C,0x00
0x024D,0x00
0x024E,0x00
0x024F,0x00
0x0250,0x00
0x0251,0x00
0x0252,0x00
0x0253,0x00
0x0254,0x00
0x0255,0x00
0x0256,0x00
0x0257,0x00
0x0258,0x00
0x0259,0x00
0x025A,0x00
0x025B,0x00
0x025C,0x00
0x025D,0x00
0x025E,0x00
0x025F,0x00
0x0260,0x00
0x0261,0x00
0x0262,0x00
0x0263,0x00
0x0264,0x00
0x0268,0x00
0x0269,0x00
0x026A,0x00
0x026B,0x54
0x026C,0x4C
0x026D,0x55
0x026E,0x31
0x026F,0x45
0x0270,0x5F
0x0271,0x30
0x0272,0x31
0x0302,0x00
0x0303,0x00
0x0304,0x00
0x0305,0x80
0x0306,0x54
0x0307,0x00
0x0308,0x00
0x0309,0x00
0x030A,0x00
0x030B,0x80
0x030C,0x00
0x030D,0x00
0x030E,0x00
0x030F,0x00
0x0310,0x00
0x0311,0x00
0x0312,0x00
0x0313,0x00
0x0314,0x00
0x0315,0x00
0x0316,0x00
0x0317,0x00
0x0318,0x00
0x0319,0x00
0x031A,0x00
0x031B,0x00
0x031C,0x00
0x031D,0x00
0x031E,0x00
0x031F,0x00
0x0320,0x00
0x0321,0x00
0x0322,0x00
0x0323,0x00
0x0324,0x00
0x0325,0x00
0x0326,0x00
0x0327,0x00
0x0328,0x00
0x0329,0x00
0x032A,0x00
0x032B,0x00
0x032C,0x00
0x032D,0x00
0x032E,0x00
0x032F,0x00
0x0330,0x00
0x0331,0x00
0x0332,0x00
0x0333,0x00
0x0334,0x00
0x0335,0x00
0x0336,0x00
0x0337,0x00
0x0338,0x00
0x0339,0x1F
0x033B,0x00
0x033C,0x00
0x033D,0x00
0x033E,0x00
0x033F,0x00
0x0340,0x00
0x0341,0x00
0x0342,0x00
0x0343,0x00
0x0344,0x00
0x0345,0x00
0x0346,0x00
0x0347,0x00
0x0348,0x00
0x0349,0x00
0x034A,0x00
0x034B,0x00
0x034C,0x00
0x034D,0x00
0x034E,0x00
0x034F,0x00
0x0350,0x00
0x0351,0x00
0x0352,0x00
0x0353,0x00
0x0354,0x00
0x0355,0x00
0x0356,0x00
0x0357,0x00
0x0358,0x00
0x0359,0x00
0x035A,0x00
0x035B,0x00
0x035C,0x00
0x035D,0x00
0x035E,0x00
0x035F,0x00
0x0360,0x00
0x0361,0x00
0x0362,0x00
0x0487,0x00
0x0502,0x01
0x0508,0x14
0x0509,0x23
0x050A,0x0C
0x050B,0x0B
0x050C,0x03
0x050D,0x3F
0x050E,0x17
0x050F,0x2B
0x0510,0x09
0x0511,0x08
0x0512,0x03
0x0513,0x3F
0x0515,0x00
0x0516,0x00
0x0517,0x00
0x0518,0x00
0x0519,0xA4
0x051A,0x02
0x051B,0x00
0x051C,0x00
0x051D,0x00
0x051E,0x00
0x051F,0x80
0x0521,0x21
0x052A,0x05
0x052B,0x01
0x052C,0x0F
0x052D,0x03
0x052E,0x19
0x052F,0x19
0x0531,0x00
0x0532,0x42
0x0533,0x03
0x0534,0x00
0x0535,0x00
0x0536,0x08
0x0537,0x00
0x0538,0x00
0x0539,0x00
0x0802,0x35
0x0803,0x05
0x0804,0x00
0x090E,0x02
0x0943,0x00
0x0949,0x07
0x094A,0x07
0x0A02,0x00
0x0A03,0x01
0x0A04,0x01
0x0A05,0x01
0x0B44,0x2F
0x0B46,0x00
0x0B47,0x00
0x0B48,0x08
0x0B4A,0x1E
0x0514,0x01
0x001C,0x01
0x0B24,0xDB
0x0B25,0x02
projects/TLU_v1e/scripts/localConf.conf 0 → 100644
+ 90
− 0
View file @ 1ed6c0ee
[Producer.fmctlu]
verbose= 1
confid= 20170626
delayStart= 1000
# HDMI pin direction:
# 4-bits to determine direction of HDMI pins
# 1-bit for the clock pair
# 0= pins are not driving signals, 1 pins drive signals (outputs)
HDMI1_set= 0x7
HDMI2_set= 0x7
HDMI3_set= 0x7
HDMI4_set= 0x7
HDMI1_clk = 1
HDMI2_clk = 1
HDMI3_clk = 1
HDMI4_clk = 1
# Enable/disable differential LEMO CLOCK
LEMOclk = 1
# Set delay and stretch for trigger pulses
in0_STR = 1
in0_DEL = 0
in1_STR = 1
in1_DEL = 0
in2_STR = 1
in2_DEL = 0
in3_STR = 1
in3_DEL = 0
in4_STR = 1
in4_DEL = 0
in5_STR = 1
in5_DEL = 0
#
trigMaskHi = 0x00000000
trigMaskLo = 0x00000002
#
#### DAC THRESHOLD
DACThreshold0 = -0.12
DACThreshold1 = -0.12
DACThreshold2 = -0.12
DACThreshold3 = -0.12
DACThreshold4 = -0.12
DACThreshold5 = -0.12
# Define which DUTs are ON
DutMask = F
# Define mode of DUT (00 EUDET, 11 AIDA)
DUTMaskMode= 0xFFFFFFFF
# Allow asynchronous veto
DUTMaskModeModifier= 0x0
# Ignore busy from a specific DUT
DUTIgnoreBusy = F
# Ignore the SHUTTER veto on a specific DUT
DUTIgnoreShutterVeto = 0x0
# Generate internal triggers (in Hz, 0= no triggers)
InternalTriggerFreq = 1000000
ShutterControl = 3
InternalShutterInterval = 1024
ShutterOnTime = 200
ShutterVetoOffTime = 300
ShutterOffTime = 400
[LogCollector.log]
# Currently, all LogCollectors have a hardcoded runtime name: log
# nothing
[DataCollector.my_dc]
EUDAQ_MON=my_mon
# send assambled event to the monitor with runtime name my_mon;
EUDAQ_FW=native
# the format of data file
EUDAQ_FW_PATTERN=$12D_run$6R$X
# the name pattern of data file
# the $12D will be converted a data/time string with 12 digits.
# the $6R will be converted a run number string with 6 digits.
# the $X will be converted the suffix name of data file.
[Monitor.my_mon]
EX0_ENABLE_PRINT=0
EX0_ENABLE_STD_PRINT=0
EX0_ENABLE_STD_CONVERTER=1
projects/TLU_v1e/scripts/localIni.ini 0 → 100644
+ 43
− 0
View file @ 1ed6c0ee
[Producer.fmctlu]
initid= 20170703
verbose = 1
ConnectionFile= "file://./../user/eudet/misc/fmctlu_connection.xml"
DeviceName="fmctlu.udp"
TLUmod= "1e"
# number of HDMI inputs, leave 4 even if you only use fewer inputs
nDUTs = 4
nTrgIn = 6
# 0= False (Internal Reference OFF), 1= True
intRefOn = 0
VRefInt = 2.5
VRefExt = 1.3
# I2C address of the bus expander on Enclustra FPGA
I2C_COREEXP_Addr = 0x21
# I2C address of the Si5345
I2C_CLK_Addr = 0x68
# I2C address of 1st AD5665R
I2C_DAC1_Addr = 0x13
# I2C address of 2nd AD5665R
I2C_DAC2_Addr = 0x1F
# address of unique Id number EEPROM
I2C_ID_Addr = 0x50
#I2C address of 1st expander PCA9539PW
I2C_EXP1_Addr = 0x74
#I2C address of 2st expander PCA9539PW
I2C_EXP2_Addr = 0x75
##CONFCLOCK 0= skip clock configuration, 1= configure si5345
CONFCLOCK= 0
CLOCK_CFG_FILE = /users/phpgb/workspace/myFirmware/AIDA/TLU_v1e/scripts/localClock.txt
[LogCollector.log]
# Currently, all LogCollectors have a hardcoded runtime name: log
EULOG_GUI_LOG_FILE_PATTERN = myexample_$12D.log
# the $12D will be converted a data/time string with 12 digits.
[DataCollector.my_dc]
# nothing
[Monitor.my_mon]
# nothing
projects/TLU_v1e/scripts/packages/AD5665R.py 0 → 100644
+ 45
− 0
View file @ 1ed6c0ee
# -*- coding: utf-8 -*-
import uhal
from I2CuHal import I2CCore
import StringIO
class AD5665R:
#Class to configure the DAC modules
def __init__(self, i2c, slaveaddr=0x1F):
self.i2c = i2c
self.slaveaddr = slaveaddr
def setIntRef(self, intRef=False, verbose=False):
mystop=True
if intRef:
cmdDAC= [0x38,0x00,0x01]
else:
cmdDAC= [0x38,0x00,0x00]
self.i2c.write( self.slaveaddr, cmdDAC, mystop)
if verbose:
print "DAC int ref:", intRef
def writeDAC(self, dacCode, channel, verbose=False):
#Vtarget is the required voltage, channel is the DAC channel to target
#intRef indicates whether to use the external voltage reference (True)
#or the internal one (False).
print "\tDAC value:" , hex(dacCode)
if channel<0 or channel>7:
print "writeDAC ERROR: channel",channel,"not in range 0-7 (bit mask)"
return -1
if dacCode<0:
print "writeDAC ERROR: value",dacCode,"<0. Default to 0"
dacCode=0
elif dacCode>0xFFFF :
print "writeDAC ERROR: value",dacCode,">0xFFFF. Default to 0xFFFF"
dacCode=0xFFFF
sequence=[( 0x18 + ( channel &0x7 ) ) , int(dacCode/256)&0xff , int(dacCode)&0xff]
print "\tWriting DAC string:", sequence
mystop= False
self.i2c.write( self.slaveaddr, sequence, mystop)
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