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Commit 001e9832 authored by David Cussans's avatar David Cussans
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* Replaced the old T0_Shutter_Iface_rtl.vhd with new shutter generator 

* Moved counterWithResetPreload_rtl.vhd to counterWithResetPreset_rtl.vhd
* Changed dep file to include new files.
* Minor change to dualSERDES_1to4_rtl.vhd to hopefully remove a warning message
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components/tlu/firmware/hdl/SyncGeneratorIPBus_rtl.vhd deleted 100644 → 0
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View file @ dbbf5741
--=============================================================================
--! @file syncGenerator_rtl.vhd
--=============================================================================
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- unit name: syncGenerator
--
--============================================================================
--! Entity declaration for syncGenerator
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.ipbus.all;
use work.ipbus_reg_types.all;
--! Include math_real to get ceil and log2
-- use IEEE.math_real.all;
--! @brief Generates a sync signal for, eg. KPix
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date April 2018
--
--! @version v0.1
--
-------------------------------------------------------------------------------
--! @details
--! Address map:
--! 0x0 Control (bit-0 : high = shutter pulses on)
--! 0x1 Select source
--! 0x2 Internal trig generator period ( units = number of strobe pulses)
--! 0x3 Shutter on time - time between input trigger being received and shutter asserted(T1)
--! 0x4 Veto off time - time between input trigger and veto being de-asserted(T2)
--! 0x5 Shutter off time - time at which shutter de-asserted(T3)
--
--! \n\n<b>Last changes:</b>\n
--!
ENTITY syncGeneratorIPBus IS
GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits in counter
g_IPBUS_WIDTH : integer := 32; --! Width of IPBus data bus
g_NUM_TRIG_SOURCES : integer := 4 --! Number of input trigger sources.
);
PORT
(
-- Input signals
clock_i: IN STD_LOGIC; --! rising edge active clock
reset_i: IN STD_LOGIC; --! Active high. syncronous with rising clk
strobe_i: IN STD_LOGIC; --! one strobe pulse per 4 clock cycles
trigger_sources_i: IN STD_LOGIC_VECTOR(g_NUM_TRIG_SOURCES-1 downto 0); --! array of possible trigger trigger_sources
--! IPBus signals
ipb_clk_i: in std_logic;
ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus;
--! Output Signals
shutter_o: OUT STD_LOGIC;
trigger_veto_o: OUT STD_LOGIC
);
END syncGeneratorIPBus;
ARCHITECTURE rtl OF syncGeneratorIPBus IS
--constant c_SELWIDTH : integer := integer(ceil(log2(real(g_NUM_TRIG_SOURCES))));
signal s_sel : integer := 0;
signal s_counter_value: std_logic_vector(g_COUNTER_WIDTH downto 0); -- One wider that comparator values.
signal s_trigger, s_counter_enable, s_reset_counter: std_logic :='0';
signal s_trigger_source_select: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
signal s_counter_lt_t1 , s_counter_lt_t2 , s_counter_lt_t3 , s_counter_gt_cycle : std_logic := '0';
signal s_shutter , s_veto : std_logic := '0';
signal s_threshold_t1,s_threshold_t3,s_threshold_t2, s_internal_cycle_length : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
signal s_enable_sequence : std_logic ; --! take high to enable sequence
signal s_enable_internal_cycle : std_logic ; --! take high to enable internal sequence
-- signal s_internal_cycle_length : STD_LOGIC_VECTOR(g_IPBUS_WIDTH-1 downto 0); --! Length of internally generated strobe cycle.
constant c_NUM_CTRL_REGS : integer := 6;
constant c_NUM_STAT_REGS : integer := 1;
signal s_ipbus_statusregs: ipb_reg_v(c_NUM_STAT_REGS - 1 downto 0) := (others => (others => '0'));
signal s_ipbus_controlregs: ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0);
constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0) := (others => (others => '1'));
begin
cmp_SyncGen: entity work.syncGenerator
generic map (
g_COUNTER_WIDTH => g_COUNTER_WIDTH ,
g_IPBUS_WIDTH => g_IPBUS_WIDTH ,
g_NUM_TRIG_SOURCES => g_NUM_TRIG_SOURCES )
port map (
clock_i => clock_i,
reset_i => reset_i,
strobe_i => strobe_i,
trigger_sources_i => trigger_sources_i,
trigger_source_select_i => s_trigger_source_select,
threshold_t1_i => s_threshold_t1,
threshold_t2_i => s_threshold_t2,
threshold_t3_i => s_threshold_t3,
enable_sequence_i => s_enable_sequence,
internal_cycle_length_i => s_internal_cycle_length,
enable_internal_cycle_i => s_enable_internal_cycle,
shutter_o => shutter_o,
trigger_veto_o => trigger_veto_o );
cmp_ipbusReg: entity work.ipbus_syncreg_v
generic map(
N_CTRL => c_NUM_CTRL_REGS,
N_STAT => c_NUM_STAT_REGS
)
port map (
clk => ipb_clk_i,
rst => reset_i,
ipb_in => ipb_in,
ipb_out => ipb_out,
slv_clk => clock_i,
d => s_ipbus_statusregs,
q=> s_ipbus_controlregs,
qmask => c_ipbus_qmask,
stb => open,
rstb => open
);
s_enable_sequence <= s_ipbus_controlregs(0)(0);
s_enable_internal_cycle <= s_ipbus_controlregs(0)(1);
s_trigger_source_select <= s_ipbus_controlregs(1);
s_threshold_t1 <= s_ipbus_controlregs(3);
s_threshold_t2 <= s_ipbus_controlregs(4);
s_threshold_t3 <= s_ipbus_controlregs(5);
s_internal_cycle_length <= s_ipbus_controlregs(2);
END rtl;
components/tlu/firmware/hdl/T0_Shutter_Iface_rtl.vhd
+ 150
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--=============================================================================
--! @file T0_Shutter_Iface_rtl.vhd --! @file T0_Shutter_Iface_rtl.vhd
--=============================================================================
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- unit name: T0_Shutter_Iface
-- --
--============================================================================
--! Entity declaration for T0_Shutter_Iface
--============================================================================
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
library unisim;
use unisim.VComponents.all;
USE work.ipbus.all;
use work.ipbus.all;
use work.ipbus_reg_types.all; use work.ipbus_reg_types.all;
--! @brief Simple module to generate T0 and shutter signals under IPBus control --! @brief Generates T0 signal and shutter signals for, eg. KPix
--! Similar interface to TPx3_iface_rtl.vhd --
--! @author David Cussans , David.Cussans@bristol.ac.uk
-- --
--! @date April 2018
--
--! @version v0.1
--
-------------------------------------------------------------------------------
--! @details --! @details
--! \n \n IPBus address map: --! \n IPBus Address map:
--! \li 00 - Activate shutter. Bit 0. Shutter is active if bit-0=1 , else always 0 --! \li 0x0 Control (bit-0 : high = shutter pulses on)
--! \li 01 - T0 write to pulse T0. Four cycles of clk_4x ( one cycle of clock sent to DUTs) --! \li 0x1 Select source
--! \li 10 - Delay from signal from accelerator to shutter signal. --! \li 0x2 Internal trig generator period ( units = number of strobe pulses)
--! \li 11 - Which trigger signal to regard as accelerator input. Not currently used. --! \li 0x3 Shutter on time - time between input trigger being received and shutter asserted(T1)
--! @author David Cussans --! \li 0x4 Veto off time - time between input trigger and veto being de-asserted(T2)
--! \li 0x5 Shutter off time - time at which shutter de-asserted(T3)
entity T0_Shutter_Iface is --! \li 0x8 Pulse T0
generic ( --! \n\n<b>Last changes:</b>\n
g_NUM_ACCELERATOR_SIGNALS: positive := 6 --! Number of hardware signals. --!
);
port (
clk_4x_i : in std_logic; --! system clock
clk_4x_strobe_i : in std_logic; --! strobes high for one cycle every 4 of clk_4x ENTITY T0_Shutter_Iface IS
accelerator_signals_i : in std_logic_vector(g_NUM_ACCELERATOR_SIGNALS-1 downto 0); --! hardware signals from accelerator GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits in counter
T0_o : out std_logic; --! T0 signal retimed onto system clock g_IPBUS_WIDTH : integer := 32; --! Width of IPBus data bus
shutter_o : out std_logic; --! shutter signal retimed onto system clock g_NUM_TRIG_SOURCES : integer := 4 --! Number of input trigger sources.
ipbus_clk_i : IN std_logic; --! IPBus system clock );
ipbus_i : IN ipb_wbus; PORT
ipbus_o : OUT ipb_rbus (
); -- Input signals
clock_i: IN STD_LOGIC; --! rising edge active clock
end entity T0_Shutter_Iface; reset_i: IN STD_LOGIC; --! Active high. syncronous with rising clk
strobe_i: IN STD_LOGIC; --! one strobe pulse per 4 clock cycles
architecture rtl of T0_Shutter_Iface is trigger_sources_i: IN STD_LOGIC_VECTOR(g_NUM_TRIG_SOURCES-1 downto 0); --! array of possible trigger trigger_sources
signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0'; --! signal after IBufDS and sampled onto clk_4x --! IPBus signals
signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i ipb_clk_i: in std_logic;
signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus;
signal s_shutter , s_shutter_d1 , s_shutter_d2 : std_logic := '0'; --! signal after IBufDS and sampled onto clk_4x
signal s_shutter_delay : std_logic_vector(ipbus_i.ipb_wdata'range); --! --! Output Signals
signal s_T0_ipbus , s_T0_ipbus_d1 , s_T0_ipbus_d2: std_logic := '0'; --! T0 sync signal shutter_o: OUT STD_LOGIC; --! Shutter signal.
signal s_shutter_ipbus , s_shutter_ipbus_d1 , s_shutter_ipbus_d2 , s_shutter_ipbus_enable: std_logic := '0'; -- Signals that get combined with incoming hardware signals from TPIx3 telescope trigger_veto_o: OUT STD_LOGIC; --! Goes high when shutter vetoes triggers
signal s_accelerator_trigger_shutter : std_logic := '0'; --! Taking this line high triggers a shutter T0_o --! T0 synchronization pulse
);
signal s_ipbus_ack : std_logic := '0'; -- used to produce a delayed IPBus ack signal END T0_Shutter_Iface;
signal s_counting_down : std_logic ; -- high whilst counting down then goes low.
begin -- architecture rtl
-------------------- ARCHITECTURE rtl OF T0_Shutter_Iface IS
ipbus_write: process (ipbus_clk_i)
begin -- process ipb_clk_i signal s_sel : integer := 0;
if rising_edge(ipbus_clk_i) then signal s_counter_value: std_logic_vector(g_COUNTER_WIDTH downto 0); -- One wider that comparator values.
s_T0_ipbus <= '0'; signal s_trigger, s_counter_enable, s_reset_counter: std_logic :='0';
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1') then
case ipbus_i.ipb_addr(1 downto 0) is signal s_trigger_source_select: std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
when "00" => s_shutter_ipbus_enable <= ipbus_i.ipb_wdata(0) ; -- Set IPBus shutter enable signal s_counter_lt_t1 , s_counter_lt_t2 , s_counter_lt_t3 , s_counter_gt_cycle : std_logic := '0';
when "01" => s_T0_ipbus <= '1'; -- set T0 signal high signal s_shutter , s_veto : std_logic := '0';
when "10" => s_shutter_delay <= ipbus_i.ipb_wdata; signal s_threshold_t1,s_threshold_t3,s_threshold_t2, s_internal_cycle_length : std_logic_vector(g_IPBUS_WIDTH-1 downto 0);
when others => null;
end case;
end if;
s_ipbus_ack <= ipbus_i.ipb_strobe and not s_ipbus_ack;
end if;
end process ipbus_write;
ipbus_o.ipb_ack <= s_ipbus_ack; signal s_enable_sequence : std_logic ; --! take high to enable sequence
ipbus_o.ipb_err <= '0'; signal s_enable_internal_cycle : std_logic ; --! take high to enable internal sequence
-- signal s_internal_cycle_length : STD_LOGIC_VECTOR(g_IPBUS_WIDTH-1 downto 0); --! Length of internally generated strobe cycle.
------------------ constant c_NUM_CTRL_REGS : integer := 8;
-- Bodge - just wire up trigger input 5 to the accelerator signal for now. constant c_NUM_STAT_REGS : integer := 1;
s_accelerator_trigger_shutter <= accelerator_signals_i(g_NUM_ACCELERATOR_SIGNALS-1); signal s_ipbus_statusregs: ipb_reg_v(c_NUM_STAT_REGS - 1 downto 0) := (others => (others => '0'));
signal s_ipbus_controlregs: ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0);
cmp_delayPulse: entity work.DelayPulse4x constant c_ipbus_qmask : ipb_reg_v(c_NUM_CTRL_REGS - 1 downto 0) := (others => (others => '1'));
generic map (
g_MAX_WIDTH => s_shutter_delay'length ) constant c_T0_address : std_logic_vector(3 downto 0) := "1000"; --! Write here for T0 pulse
begin
cmp_SyncGen: entity work.syncGenerator
generic map (
g_COUNTER_WIDTH => g_COUNTER_WIDTH ,
g_IPBUS_WIDTH => g_IPBUS_WIDTH ,
g_NUM_TRIG_SOURCES => g_NUM_TRIG_SOURCES )
port map (
clock_i => clock_i,
reset_i => reset_i,
strobe_i => strobe_i,
trigger_sources_i => trigger_sources_i,
trigger_source_select_i => s_trigger_source_select,
threshold_t1_i => s_threshold_t1,
threshold_t2_i => s_threshold_t2,
threshold_t3_i => s_threshold_t3,
enable_sequence_i => s_enable_sequence,
internal_cycle_length_i => s_internal_cycle_length,
enable_internal_cycle_i => s_enable_internal_cycle,
shutter_o => shutter_o,
trigger_veto_o => trigger_veto_o );
cmp_ipbusReg: entity work.ipbus_syncreg_v
generic map(
N_CTRL => c_NUM_CTRL_REGS,
N_STAT => c_NUM_STAT_REGS
)
port map ( port map (
clk_4x_i => clk_4x_i, clk => ipb_clk_i,
clk_4x_strobe_i => clk_4x_strobe_i, rst => reset_i,
delay_cycles_i => s_shutter_delay, ipb_in => ipb_in,
pulse_i => s_accelerator_trigger_shutter, ipb_out => ipb_out,
pulse_o => shutter_o slv_clk => clock_i,
d => s_ipbus_statusregs,
q=> s_ipbus_controlregs,
qmask => c_ipbus_qmask,
stb => open,
rstb => open
); );
s_enable_sequence <= s_ipbus_controlregs(0)(0);
s_enable_internal_cycle <= s_ipbus_controlregs(0)(1);
s_trigger_source_select <= s_ipbus_controlregs(1);
s_threshold_t1 <= s_ipbus_controlregs(3);
s_threshold_t2 <= s_ipbus_controlregs(4);
s_threshold_t3 <= s_ipbus_controlregs(5);
s_internal_cycle_length <= s_ipbus_controlregs(2);
-- A bodge. I can't figure out which standard IPBus register generates a
-- pulse, so put this logic in parallel.
--------------------
ipbus_generateT0: process (ipbus_clk_i)
begin -- process ipb_clk_i
if rising_edge(ipbus_clk_i) then
if (ipbus_i.ipb_strobe = '1' and ipbus_i.ipb_write = '1' and ipbus_i.ipb_addr(3 downto 0) = c_T0_address ) then
s_T0_ipbus <= '1'; -- set T0 signal high
else
s_T0_ipbus <= '0';
end if;
--! Retime T0 generated by IPBus onto clk_4x and align with strobe end if;
cmp_T0_retime: entity work.stretchPulse4x end process ipbus_generateT0;
port map (
clk_4x_i => clk_4x_i,
clk_4x_strobe_i => clk_4x_strobe_i,
pulse_i => s_T0_ipbus,
pulse_o => T0_o);
--! Retime T0 generated by IPBus onto clk_4x and align with strobe
cmp_T0_retime: entity work.stretchPulse4x
port map (
clk_4x_i => clock_i,
clk_4x_strobe_i => strobe_i,
pulse_i => s_T0_ipbus,
pulse_o => T0_o);
end architecture rtl; END rtl;
components/tlu/firmware/hdl/counterWithResetPreload_rtl.vhd deleted 100644 → 0
+ 0
− 87
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--=============================================================================
--! @file counterWithResetPreset_rtl.vhd
--=============================================================================
-------------------------------------------------------------------------------
-- --
-- University of Bristol, High Energy Physics Group.
-- --
------------------------------------------------------------------------------- --
-- unit name: counterWithResetPreset (counterWithResetPreset / rtl)
--
--============================================================================
--! Entity declaration for counterWithResetPreset
--============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
--! @brief Simple counter with synchronous reset and top-bit preload
--
--! @author David Cussans , David.Cussans@bristol.ac.uk
--
--! @date Feb\2012
--
--! @version v0.1
--
-------------------------------------------------------------------------------
--! @details
--! \n\n<b>Last changes:</b>\n
--! 5/Mar/12 DGC Changed to use numeric_std\n
--! 26/Feb/14 DGC Added registers to output to aid timing closure.
--!
ENTITY counterWithResetPreset IS
GENERIC (g_COUNTER_WIDTH : integer := 32; --! Number of bits
g_OUTPUT_REGISTERS : integer := 4 --! Number of output registers. Minumum =1. Aids timing closure.
);
PORT
(
clock_i: IN STD_LOGIC; --! rising edge active clock
reset_i: IN STD_LOGIC; --! Active high. synchronous with rising clk. Takes output to 0
preset_i: IN STD_LOGIC; --! Active high. synchronous with rising clk. Takes highest bit to 1
enable_i: IN STD_LOGIC; --! counts when enable=1
result_o: OUT STD_LOGIC_VECTOR ( g_COUNTER_WIDTH-1 downto 0) --! Unsigned integer output
);
END counterWithResetPreset;
ARCHITECTURE rtl OF counterWithResetPreset IS
type t_register_array is array(natural range <>) of UNSIGNED ( g_COUNTER_WIDTH-1 downto 0) ; -- --! Array of arrays for output register...
signal s_output_registers : t_register_array(g_OUTPUT_REGISTERS downto 0) := ( others => ( others => '0')); -- --! Output registers.
BEGIN
--! Process to count up from zero when enable_i is high.
p_counter: PROCESS (clock_i)
BEGIN
IF rising_edge(clock_i) THEN
IF (reset_i = '1') THEN
s_output_registers(0) <= (others => '0');
ELSIF (preset_i='1') THEN
s_output_registers(0)(g_COUNTER_WIDTH-1) <= '1'; -- Preload highest bit to '1'
ELSIF (enable_i='1') THEN
s_output_registers(0) <= s_output_registers(0) + 1;
END IF;
END IF;
END PROCESS p_counter;
--! Generate some output registers. Number controlled by g_OUTPUT_REGISTERS
generate_registers: for v_register in 1 to g_OUTPUT_REGISTERS generate
--! An individual register
p_outputRegister: process (clock_i)
begin -- process p_outputRegister
if rising_edge(clock_i) then
s_output_registers( v_register) <=
s_output_registers( v_register-1);
end if;
end process p_outputRegister;
end generate generate_registers; -- v_register
--! Copy the (registered) result to the output
result_o <= STD_LOGIC_VECTOR(s_output_registers(g_OUTPUT_REGISTERS));
END rtl;
components/tlu/firmware/hdl/trigger/dualSERDES_1to4_rtl.vhd
+ 2
− 2
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...@@ -315,7 +315,7 @@ BEGIN ...@@ -315,7 +315,7 @@ BEGIN
DATA_RATE => "DDR", DATA_RATE => "DDR",
DATA_WIDTH => 4, DATA_WIDTH => 4,
INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
IOBDELAY => "BOTH", --same as above IOBDELAY => "IFD", -- see table 3-4 in UG471 (v1.9)
SERDES_MODE => "MASTER", SERDES_MODE => "MASTER",
NUM_CE => 1 NUM_CE => 1
) )
...@@ -378,7 +378,7 @@ BEGIN ...@@ -378,7 +378,7 @@ BEGIN
DATA_RATE => "DDR", DATA_RATE => "DDR",
DATA_WIDTH => 4, DATA_WIDTH => 4,
INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct INTERFACE_TYPE=> "NETWORKING", --Not sure this is correct
IOBDELAY => "BOTH", --same as above IOBDELAY => "IFD", -- see table 3-4 in UG471 (v1.9)
SERDES_MODE => "MASTER", SERDES_MODE => "MASTER",
NUM_CE => 1 NUM_CE => 1
) )
......
projects/TLU_v1e/addr_table/TLUaddrmap.xml
+ 7
− 2
View file @ 001e9832
...@@ -17,8 +17,13 @@ ...@@ -17,8 +17,13 @@
</node> </node>
<node id="Shutter" address="0x2000" description="Shutter/T0 control" fwinfo="endpoint;width=4"> <node id="Shutter" address="0x2000" description="Shutter/T0 control" fwinfo="endpoint;width=4">
<node id="ShutterStateW" address="0x0" permission="w" description=""/> <node id="ControlW" address="0x0" permission="w" description="Bit-0 controls if shutter pulses are active. 1 = active"/>
<node id="PulseT0" address="0x1" permission="w" description=""/> <node id="ShutterSelectW" address="0x1" permission="w" description="Selects which input is used to trigger shutter"/>
<node id="InternalShutterPeriodW" address="0x2" permission="w" description="Internal trig generator period ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x3" permission="w" description="Time between input trigger being received and shutter asserted(T1) ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x4" permission="w" description="time between input trigger and veto being de-asserted(T2) ( units = number of strobe pulses)"/>
<node id="ShutterOnTimeW" address="0x5" permission="w" description="time at which shutter de-asserted(T3) ( units = number of strobe pulses)"/>
<node id="PulseT0" address="0x8" permission="w" description="Writing to Bit-0 of this register causes sync line to pulse for one strobe-pulse interval"/>
</node> </node>
<!-- I2C registers. Tested ok.--> <!-- I2C registers. Tested ok.-->
<node id="i2c_master" address="0x3000" description="I2C Master interface" fwinfo="endpoint;width=3"> <node id="i2c_master" address="0x3000" description="I2C Master interface" fwinfo="endpoint;width=3">
......
projects/TLU_v1e/firmware/cfg/tlu_1e.dep
+ 2
− 0
View file @ 001e9832
...@@ -17,6 +17,8 @@ src -c components/tlu logic_clocks_rtl.vhd ...@@ -17,6 +17,8 @@ src -c components/tlu logic_clocks_rtl.vhd
src -c components/tlu trigger/triggerInputs_newTLU_rtl.vhd src -c components/tlu trigger/triggerInputs_newTLU_rtl.vhd
src -c components/tlu eventFormatter_rtl.vhd src -c components/tlu eventFormatter_rtl.vhd
src -c components/tlu T0_Shutter_Iface_rtl.vhd src -c components/tlu T0_Shutter_Iface_rtl.vhd
src -c components/tlu SyncGenerator_rtl.vhd
src -c components/tlu counterWithResetPreset_rtl.vhd
src -c components/tlu counterDownGated_rtl.vhd src -c components/tlu counterDownGated_rtl.vhd
src -c components/tlu delayPulse4x_rtl.vhd src -c components/tlu delayPulse4x_rtl.vhd
src -c components/tlu stretchPulse4x_rtl.vhd src -c components/tlu stretchPulse4x_rtl.vhd
......
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