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AIDA-2020 TLU - Gateware
Commit a8cb830a authored by David Cussans's avatar David Cussans
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Removed unused logic. Tidied up formatting. Changed version number

parent d3f83532
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Showing with 66 additions and 88 deletions
hdl/common/eventBuffer_rtl.vhd
View file @ a8cb830a
......@@ -80,12 +80,8 @@ END ENTITY eventBuffer ;
ARCHITECTURE rtl OF eventBuffer IS
-- write addr count width = 13 , read addr count = 14.
--! Counters for input and ouput to/from FIFO
signal s_wr_data_count , s_wr_data_count_reg : std_logic_vector(g_WRITE_COUNTER_WIDTH-1 downto 0) := (others =>'0');
signal s_rd_data_count : std_logic_vector(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0');
--signal s_fifo_fill_level : unsigned(g_READ_COUNTER_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_fifo_fill_level : std_logic_vector(g_IPBUS_WIDTH-1 downto 0) := (others =>'0'); -- read-counter - 2*write_count
signal s_write_strobe : std_logic := '0';
......@@ -128,7 +124,6 @@ BEGIN
-- Register data onto IPBus clock domain to ease timing closure.
s_fifo_status_ipb <= X"000000" & "000" & s_fifo_prog_full & s_fifo_full & s_fifo_almost_full & s_fifo_almost_empty & s_fifo_empty;
--s_fifo_fill_level_d1 <= X"0000" & "00" & std_logic_vector(s_fifo_fill_level);
s_fifo_fill_level <= X"0000" & s_rd_data_count;
end if;
end process ipbus_write;
......@@ -155,31 +150,10 @@ BEGIN
empty => s_fifo_empty,
almost_empty => s_fifo_almost_empty,
rd_data_count => s_rd_data_count,
wr_data_count => s_wr_data_count,
prog_full => s_fifo_prog_full
);
buffer_full_o <= s_fifo_prog_full;
-- Transfer write-data-count to read clock domain
register_counter_inst : entity work.registerCounter
generic map (
g_DATA_WIDTH => g_WRITE_COUNTER_WIDTH)
port map (
clk_input_i => clk_4x_logic_i,
data_i => s_wr_data_count,
data_o => s_wr_data_count_reg,
clk_output_i => ipbus_clk_i
);
----! Calculate the number of words in the FIFO .
---- (only valid if no buffer overflow.)
---- Each input word (64 bits) is the same as two output words (32 bits) so
---- multiply s_wr_data_count by 2 before subraction
--! wr_data_count and rd_data_count provide exactly the same information but in different clock domains
--s_fifo_fill_level <= (unsigned(std_logic_vector(s_wr_data_count_reg) & "0") - unsigned(s_rd_data_count));
--s_fifo_fill_level <= unsigned(s_rd_data_count);
END ARCHITECTURE rtl;
hdl/common/eventFormatter_rtl.vhd
View file @ a8cb830a
......@@ -40,6 +40,8 @@
--! \n
--! Add backpressure output if short FIFOs fill up? But many inputs won't
--! respond - e.g. scintillator inputs. This data will be lost....
--! some ports are redundant - e.g. trigger counter, others confusingly
--! labelled. Sort this out..
--------------------------------------------------------------------------------
--
-- Created using using Mentor Graphics HDL Designer(TM) 2010.3 (Build 21)
......@@ -57,22 +59,22 @@ ENTITY eventFormatter IS
g_IPBUS_WIDTH : positive := 32;
g_COUNTER_TRIG_WIDTH : positive := 32;
g_COUNTER_WIDTH : positive := 12;
g_EVTTYPE_WIDTH : positive := 4; -- Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; -- Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS : positive := 4; -- Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 -- Number of trigger inputs
g_EVTTYPE_WIDTH : positive := 4; --! Width of the event type word
--g_NUM_INPUT_TYPES : positive := 4; --! Number of different input types (trigger, shutter, edge...)
g_NUM_EDGE_INPUTS : positive := 4; --! Number of edge inputs
g_NUM_TRIG_INPUTS : positive := 5 --! Number of trigger inputs
);
PORT(
clk_4x_logic_i : IN std_logic; -- ! Rising edge active
clk_4x_logic_i : IN std_logic; --! Rising edge active
ipbus_clk_i : IN std_logic;
logic_strobe_i : IN std_logic; -- ! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic; -- goes high to reset counters. Synchronous with clk_4x_logic
logic_strobe_i : IN std_logic; --! Pulses high once every 4 cycles of clk_4x_logic
logic_reset_i : IN std_logic; --! goes high to reset counters. Synchronous with clk_4x_logic
rst_fifo_i : IN std_logic; --! Reset fifos
buffer_full_i : IN std_logic; -- Buffer full signal from main buffer
buffer_full_i : in std_logic; --! Buffer full signal from main buffer
trigger_i : IN std_logic; --! goes high to load trigger data. One cycle of clk_4x_logic
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); -- high for each input that "fired"
trigger_times_i : IN t_triggerTimeArray (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! Array of trigger times ( w.r.t. logic_strobe)
trigger_inputs_fired_i : IN std_logic_vector (g_NUM_TRIG_INPUTS-1 DOWNTO 0); --! high for each input that "fired"
trigger_cnt_i : IN std_logic_vector (g_COUNTER_TRIG_WIDTH-1 DOWNTO 0);
shutter_i : IN std_logic;
......@@ -81,10 +83,10 @@ ENTITY eventFormatter IS
spill_i : IN std_logic;
spill_cnt_i : IN std_logic_vector(g_COUNTER_WIDTH-1 DOWNTO 0);
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- ! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); -- Array of edge times ( w.r.t. logic_strobe)
edge_rise_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when rising edge
edge_fall_i : IN std_logic_vector (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! High when falling edge
edge_rise_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
edge_fall_time_i : IN t_triggerTimeArray (g_NUM_EDGE_INPUTS-1 DOWNTO 0); --! Array of edge times ( w.r.t. logic_strobe)
ipbus_i : IN ipb_wbus;
ipbus_o : OUT ipb_rbus;
......@@ -137,7 +139,7 @@ ARCHITECTURE rtl OF eventFormatter IS
signal s_FIFO_rd : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals
signal s_FIFO_rd_d1 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
signal s_FIFO_rd_d2 : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO read signals delayed
signal s_FIFO_rd_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (0 =>'1',others=>'0'); --(3+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- FIFO read mask
constant c_FIFO_rd_mask : unsigned(3+g_NUM_EDGE_INPUTS-1 downto 0) := (0 =>'1',others=>'0'); --(3+g_NUM_EDGE_INPUTS-1 =>'1',others=>'0'); -- FIFO read mask
signal s_FIFO_empty : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO empty signals
signal s_FIFO_full : std_logic_vector(3+g_NUM_EDGE_INPUTS-1 downto 0) := (others=>'0'); -- FIFO full signals
signal s_FIFO_i : t_fifo_io(3+g_NUM_EDGE_INPUTS-1 downto 0) :=(others=>(others=>'0')); -- FIFO input data
......@@ -225,6 +227,7 @@ BEGIN
-- outputs: s_event_strobe_d1 , s_event_strobe_d2 , s_event_strobe_d3 , s_FIFO_rd_d , s_**_evttype
p_ff_rst: process (clk_4x_logic_i)
begin -- process p_generate_strobes
if rising_edge(clk_4x_logic_i) then
if rst_fifo_i = '1' then
s_event_strobe_d1 <= '0';
s_event_strobe_d2 <= '0';
......@@ -239,7 +242,7 @@ BEGIN
s_FIFO_rd_d1 <= (others=>'0');
s_FIFO_rd_d2 <= (others=>'0');
elsif rising_edge(clk_4x_logic_i) then
else
s_event_strobe_d1 <= trigger_i and s_enable_trigger and not s_FIFO_full(0);
s_event_strobe_d2 <= s_event_strobe_d1;
s_event_strobe_d3 <= s_event_strobe_d2;
......@@ -253,6 +256,7 @@ BEGIN
s_FIFO_rd_d1 <= s_FIFO_rd;
s_FIFO_rd_d2 <= s_FIFO_rd_d1;
end if;
end if;
end process p_ff_rst;
p_ff: process (clk_4x_logic_i)
......@@ -413,13 +417,13 @@ BEGIN
-- Mux to send the read signal to only one FIFO. Priority order: trigger, shutter, edge, spill
-- every trigger word will be read before jump to other data
p_FIFO_rd: process (rst_fifo_i, s_FIFO_empty,s_FIFO_rd_mask, buffer_full_i)
p_FIFO_rd: process (rst_fifo_i, s_FIFO_empty, buffer_full_i)
begin -- process p_generate_strobes
s_FIFO_rd <= (others=>'0');
if buffer_full_i = '0' and rst_fifo_i = '0' then
l_FIFO_rd: for i in 0 to 3+g_NUM_EDGE_INPUTS-1 loop
if s_FIFO_empty(i) = '0' then
s_FIFO_rd <= std_logic_vector(s_FIFO_rd_mask sll i);
s_FIFO_rd <= std_logic_vector(c_FIFO_rd_mask sll i);
exit l_FIFO_rd;
end if;
end loop;
......
hdl/common/ipbus_ver.vhd
View file @ a8cb830a
......@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out.ipb_rdata <= X"a5ea" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_rdata <= X"a5ed" & X"1008"; -- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out.ipb_ack <= ipbus_in.ipb_strobe;
ipbus_out.ipb_err <= '0';
......
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