adding fifo_regs and dummy_time module in wrsw_dio

a414b20d · Rafael Rodriguez · Miguel Jimenez Lopez · 77c798b6 · a414b20d · a414b20d
Commit a414b20d authored Mar 11, 2012 by Rafael Rodriguez Committed by Miguel Jimenez Lopez Apr 03, 2019
6 changed files
--- a/modules/wrsw_dio/Manifest.py
+++ b/modules/wrsw_dio/Manifest.py
+files = ["wrsw_dio_wb.vhd",
+				  "wrsw_dio.vhd",
+				  "dummy_time.vhd", 
+                                  "wrsw_dio.wb",
+                                  "wrsw_dio_wb.htm"]
--- a/modules/wrsw_dio/dummy_time.vhd
+++ b/modules/wrsw_dio/dummy_time.vhd
+-------------------------------------------------------------------------------
+-- Entity: dummy_time
+-- File: dummy_time.vhd
+-- Description: ¿?
+-- Author: Javier Diaz (jdiaz@atc.ugr.es)
+-- Date: 8 March 2012
+-- Version: 0.01
+-- To do: 
+-------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------
+--               GNU LESSER GENERAL PUBLIC LICENSE                             
+--              -----------------------------------                            
+-- This source file is free software; you can redistribute it and/or modify it
+-- under the terms of the GNU Lesser General Public License as published by the
+-- Free Software Foundation; either version 2.1 of the License, or (at your
+-- option) any later version.                           
+-- This source is distributed in the hope that it will be useful, but WITHOUT
+-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
+-- for more details. You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it from
+-- http://www.gnu.org/licenses/lgpl-2.1.html                  
+-------------------------------------------------------------------------------
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+--use IEEE.NUMERIC_STD.ALL;
+use ieee.std_logic_unsigned.all; 
+
+entity dummy_time is
+	port(clk_sys : in std_logic;           -- data output reference clock 125MHz
+	     rst_n: in std_logic; -- system reset
+	     -- utc time in seconds	
+    	     tm_utc        : out std_logic_vector(39 downto 0);
+    	     -- number of clk_ref_i cycles
+    	     tm_cycles     : out std_logic_vector(27 downto 0));
+end dummy_time;
+
+architecture Behavioral of dummy_time is
+
+	signal OneSecond: std_logic;
+	signal tm_cycles_Aux: std_logic_vector(27 downto 0);
+	signal tm_utc_Aux: std_logic_vector(39 downto 0);
+	constant MaxCountcycles1: std_logic_vector(27 downto 0) :="0111011100110101100100111111"; --125.000.000-1
+	constant MaxCountcycles2: std_logic_vector(27 downto 0) :="0111011100110101100101000000"; --125.000.000
+	constant AllOnesUTC: std_logic_vector(39 downto 0):=(others=>'1');
+begin
+---------------------------------------
+-- Process to count cycles in a second
+---------------------------------------
+
+P_CountTM_cycles:
+process(rst_n, clk_sys)
+begin
+	if(rst_n = '0') then
+		tm_cycles_Aux <= (others=>'0');
+		oneSecond <= '0';
+	elsif(rising_Edge(Clk_sys)) then
+		if (Tm_cycles_Aux /= MaxCountcycles2) then
+			tm_cycles_Aux <= tm_cycles_Aux + 1;
+		else
+			tm_cycles_Aux <= (others=>'0');
+		end if;
+		
+		if(Tm_cycles_Aux = MaxCountcycles1) then
+			OneSecond <= '1';
+		else
+			OneSecond <= '0';
+		end if;
+	end if;
+end process P_CountTM_cycles;
+
+P_CountTM_UTC:
+process(rst_n, clk_sys)
+begin
+	if(rst_n = '0') then
+		tm_utc_Aux <= (others=>'0');
+	elsif(rising_edge(Clk_sys)) then
+		if (OneSecond='1') then
+			if (tm_utc_Aux /= AllOnesUTC) then
+				tm_utc_Aux <= tm_utc_Aux + 1;
+			else
+				tm_utc_Aux <= (others=>'0');
+			end if;
+		end if;
+	end if;
+end process P_CountTM_UTC;
+
+tm_cycles <= tm_cycles_Aux;
+tm_utc <= tm_utc_Aux;
+
+end Behavioral;
+
--- a/modules/wrsw_dio/wrsw_dio.vhd
+++ b/modules/wrsw_dio/wrsw_dio.vhd
@@ -40,14 +40,12 @@ entity wrsw_dio is
  );
  port (
    clk_sys_i      : in  std_logic;
+    clk_ref_i      : in  std_logic;
    rst_n_i        : in  std_logic;
 		
-    dio_clk_p_i    : in std_logic;
-    dio_clk_n_i    : in std_logic;
-    dio_n_i        : in std_logic_vector(4 downto 0);
-    dio_p_i        : in std_logic_vector(4 downto 0);
-    dio_n_o        : out std_logic_vector(4 downto 0);
-    dio_p_o        : out std_logic_vector(4 downto 0);
+    dio_clk_i      : in std_logic;
+    dio_in_i       : in std_logic_vector(4 downto 0);
+    dio_out_o      : out std_logic_vector(4 downto 0);
    dio_oe_n_o     : out std_logic_vector(4 downto 0);
    dio_term_en_o  : out std_logic_vector(4 downto 0);
    dio_onewire_b  : inout std_logic;
@@ -138,33 +136,6 @@ architecture rtl of wrsw_dio is
  
 begin  -- rtl

-  gen_dio_iobufs : for i in 0 to 4 generate
-    U_ibuf : IBUFDS
-      generic map (
-        DIFF_TERM => true)
-      port map (
-        O  => dio_in(i),
-        I  => dio_p_i(i),
-        IB => dio_n_i(i)
-        );
-
-    U_obuf : OBUFDS
-      port map (
-        I  => dio_out(i),
-        O  => dio_p_o(i),
-        OB => dio_n_o(i)
-        );
-  end generate gen_dio_iobufs;
-
-  U_input_buffer : IBUFDS
-    generic map (
-      DIFF_TERM => true)
-    port map (
-      O  => dio_clk,
-      I  => dio_clk_p_i,
-      IB => dio_clk_n_i
-      );
-  
  U_Onewire : xwb_onewire_master
    generic map (
      g_interface_mode => CLASSIC,

--- a/modules/wrsw_dio/wrsw_dio.wb
+++ b/modules/wrsw_dio/wrsw_dio.wb
 -- -*- Mode: LUA; tab-width: 2 -*-

+
+
 peripheral {
 	 name = "Shared TX Timestamping Unit (TXTSU)";
   prefix="txtsu";
@@ -69,4 +71,4 @@ peripheral {
 		 trigger = LEVEL_1;
 	};

-};
\ No newline at end of file
+};
--- a/modules/wrsw_dio/wrsw_dio_wb.htm
+++ b/modules/wrsw_dio/wrsw_dio_wb.htm
--- a/modules/wrsw_dio/wrsw_dio_wb.vhd
+++ b/modules/wrsw_dio/wrsw_dio_wb.vhd