fecthing sources from switch hdl project

743d7690 · Javier Díaz · Miguel Jimenez Lopez · a78517b2 · 743d7690
Commit 743d7690 authored Aug 01, 2012 by Javier Díaz Committed by Miguel Jimenez Lopez Apr 03, 2019
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immed_pulse_counter.vhd modules/wrsw_dio/immed_pulse_counter.vhd +3 -2

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--- a/modules/wrsw_dio/immed_pulse_counter.vhd
+++ b/modules/wrsw_dio/immed_pulse_counter.vhd
@@ -62,7 +62,7 @@ architecture rtl of immed_pulse_counter is
  
  -- Signal for synchronization (in fact they are not so necessary for current system...)
  signal pulse_start_d0, pulse_start_d1, pulse_start_d2, pulse_start_d3 : std_logic; 
-  signal nozerolength                                                   : boolean; 
+  signal nozerolength, nozerolength_aux                                 : boolean; 
  
  -- Aux
  constant zeros : std_logic_vector(pulse_length_width-1 downto 0) := (others=>'0');  
@@ -83,8 +83,9 @@ begin  -- architecture rtl
 		pulse_start_d1<=pulse_start_d0;
 		pulse_start_d2<=pulse_start_d1;
 	   pulse_start_d3<=pulse_start_d2;
+		nozerolength_aux<=pulse_length_i/=zeros;
 		if (pulse_start_d2='1' and pulse_start_d1='0') then
-			nozerolength<=pulse_length_i/=zeros;
+			nozerolength<=nozerolength_aux;
 		end if;
    end if;		
  end process;