3.0.9 - 2022-12-14
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Added
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- hdl: bitstreams now published under https://be-cem-edl.web.cern.ch/
- doc: now published under https://be-cem-edl.web.cern.ch/
- sw: support for newer Linux kernels

Changed
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- bld: many improvements to CI
- bld: build system cleanup
- hdl: update to latest releases of all dependencies
- hdl: top-level VHDL module names are now more consistent and descriptive

Fixed
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- hdl: WR ready bit in TCR register now always shows the validity of WR time
- sw: output pulse duty cycle now properly set to 50% by default