Commit 282bc2d8 authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl: increase ISE effort to meet timing

parent c0035ded
......@@ -28,8 +28,8 @@ xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outpu
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Keep Hierarchy" "Yes"
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment