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F
FMC DEL 1ns 4cha
Commit 282bc2d8 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: increase ISE effort to meet timing

parent c0035ded
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hdl/syn/svec/syn_extra_steps.tcl
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......@@ -28,8 +28,8 @@ xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outpu
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project set "Placer Extra Effort Map" "Normal"
xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
#xilinx::project set "Keep Hierarchy" "Yes"
......
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