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FMC DEL 1ns 4cha
Commit ff2a679f authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/rtl/fd_channel_wishbone_slave: added DCR.FORCE_HI bit

parent 4130caeb
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Showing with 48 additions and 7 deletions
hdl/rtl/doc/fd_channel_regs.html
View file @ ff2a679f
......@@ -470,6 +470,23 @@ fd_channel_dcr_no_fine_o
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fd_channel_dcr_force_hi_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
......@@ -481,10 +498,10 @@ wb_ack_o
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
......@@ -1338,8 +1355,8 @@ DCR
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
FORCE_HI
</td>
</tr>
</table>
......@@ -1430,6 +1447,10 @@ FORCE_DLY
NO_FINE
</b>[<i>read/write</i>]: Disable Fine Part update
<br>write 1: disables updating of the fine part of the pulse delay to allow for producing faster signals (i.e. pulse width/spacing < 200 ns), at the cost of less accurate width/spacing control (multiple of 4 ms). <br>write 0: normal operation. Pulse width/spacing must be at least 200 ns.
<li><b>
FORCE_HI
</b>[<i>read/write</i>]: Force Output High
<br>write 1: Forces constant 1 on the output when the channel is disabled<br> write 0: Forces constant 0 on the output when the channel is disabled<br> Used for testing/calibration purposes.
</ul>
<a name="FRR"></a>
<h3><a name="sect_3_2">3.2. Fine Range Register</a></h3>
......
hdl/rtl/fd_channel_wbgen2_pkg.vhd
View file @ ff2a679f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:22 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -38,6 +38,7 @@ package fd_channel_wbgen2_pkg is
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
......@@ -61,6 +62,7 @@ package fd_channel_wbgen2_pkg is
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
......
hdl/rtl/fd_channel_wishbone_slave.vhd
View file @ ff2a679f
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:22 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -62,6 +62,7 @@ signal fd_channel_dcr_force_dly_sync0 : std_logic ;
signal fd_channel_dcr_force_dly_sync1 : std_logic ;
signal fd_channel_dcr_force_dly_sync2 : std_logic ;
signal fd_channel_dcr_no_fine_int : std_logic ;
signal fd_channel_dcr_force_hi_int : std_logic ;
signal fd_channel_frr_int : std_logic_vector(9 downto 0);
signal fd_channel_u_starth_int : std_logic_vector(7 downto 0);
signal fd_channel_u_startl_int : std_logic_vector(31 downto 0);
......@@ -112,6 +113,7 @@ begin
fd_channel_dcr_force_dly_int <= '0';
fd_channel_dcr_force_dly_int_delay <= '0';
fd_channel_dcr_no_fine_int <= '0';
fd_channel_dcr_force_hi_int <= '0';
fd_channel_frr_int <= "0000000000";
fd_channel_u_starth_int <= "00000000";
fd_channel_u_startl_int <= "00000000000000000000000000000000";
......@@ -155,6 +157,7 @@ begin
fd_channel_dcr_force_dly_int <= wrdata_reg(6);
fd_channel_dcr_force_dly_int_delay <= wrdata_reg(6);
fd_channel_dcr_no_fine_int <= wrdata_reg(7);
fd_channel_dcr_force_hi_int <= wrdata_reg(8);
end if;
rddata_reg(0) <= fd_channel_dcr_enable_int;
rddata_reg(1) <= fd_channel_dcr_mode_int;
......@@ -164,7 +167,7 @@ begin
rddata_reg(5) <= fd_channel_dcr_upd_done_sync1;
rddata_reg(6) <= 'X';
rddata_reg(7) <= fd_channel_dcr_no_fine_int;
rddata_reg(8) <= 'X';
rddata_reg(8) <= fd_channel_dcr_force_hi_int;
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -580,6 +583,8 @@ begin
-- Disable Fine Part update
regs_o.dcr_no_fine_o <= fd_channel_dcr_no_fine_int;
-- Force Output High
regs_o.dcr_force_hi_o <= fd_channel_dcr_force_hi_int;
-- Fine Range
regs_o.frr_o <= fd_channel_frr_int;
-- TAI seconds (MSB)
......
hdl/rtl/fd_channel_wishbone_slave.wb
View file @ ff2a679f
......@@ -135,6 +135,19 @@ write 0: normal operation. Pulse width/spacing must be at least 200 ns.";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Force Output High";
prefix = "FORCE_HI";
description = "write 1: Forces constant 1 on the output when the channel is disabled\
write 0: Forces constant 0 on the output when the channel is disabled\
Used for testing/calibration purposes.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......
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