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FMC DEL 1ns 4cha
Commit 4130caeb authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl/rtl/fd_main_wishbone_slave: removed unused softpll register, re-organized DDMTD readout regs

parent 29f35be5
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hdl/include/regs/fd_main_regs.vh
View file @ 4130caeb
......@@ -62,22 +62,16 @@
`define FD_CALR_CAL_DMTD 32'h00000004
`define FD_CALR_PSEL_OFFSET 3
`define FD_CALR_PSEL 32'h00000078
`define FD_CALR_DMTD_FBSEL_OFFSET 7
`define FD_CALR_DMTD_FBSEL 32'h00000080
`define FD_CALR_DMTD_TAG_OFFSET 8
`define FD_CALR_DMTD_TAG 32'h7fffff00
`define FD_CALR_DMTD_TAG_RDY_OFFSET 31
`define FD_CALR_DMTD_TAG_RDY 32'h80000000
`define ADDR_FD_SPLLR 8'h28
`define FD_SPLLR_TAG_OFFSET 0
`define FD_SPLLR_TAG 32'h000fffff
`define FD_SPLLR_TAG_RDY_OFFSET 20
`define FD_SPLLR_TAG_RDY 32'h00100000
`define FD_SPLLR_MODE_OFFSET 21
`define FD_SPLLR_MODE 32'h00200000
`define ADDR_FD_SDACR 8'h2c
`define FD_SDACR_DAC_VAL_OFFSET 0
`define FD_SDACR_DAC_VAL 32'h0000ffff
`define ADDR_FD_DMTR_IN 8'h28
`define FD_DMTR_IN_TAG_OFFSET 0
`define FD_DMTR_IN_TAG 32'h7fffffff
`define FD_DMTR_IN_RDY_OFFSET 31
`define FD_DMTR_IN_RDY 32'h80000000
`define ADDR_FD_DMTR_OUT 8'h2c
`define FD_DMTR_OUT_TAG_OFFSET 0
`define FD_DMTR_OUT_TAG 32'h7fffffff
`define FD_DMTR_OUT_RDY_OFFSET 31
`define FD_DMTR_OUT_RDY 32'h80000000
`define ADDR_FD_ADSFR 8'h30
`define ADDR_FD_ATMCR 8'h34
`define FD_ATMCR_C_THR_OFFSET 0
......@@ -125,6 +119,8 @@
`define FD_TSBCR_EMPTY 32'h00000200
`define FD_TSBCR_COUNT_OFFSET 10
`define FD_TSBCR_COUNT 32'h003ffc00
`define FD_TSBCR_RAW_OFFSET 22
`define FD_TSBCR_RAW 32'h00400000
`define ADDR_FD_TSBIR 8'h54
`define FD_TSBIR_TIMEOUT_OFFSET 0
`define FD_TSBIR_TIMEOUT 32'h000003ff
......@@ -155,6 +151,10 @@
`define ADDR_FD_TDER2 8'h70
`define FD_TDER2_PELT_DRIVE_OFFSET 0
`define FD_TDER2_PELT_DRIVE 32'hffffffff
`define ADDR_FD_TSBR_DEBUG 8'h74
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
......
hdl/rtl/doc/fd_main_regs.html
View file @ 4130caeb
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hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ 4130caeb
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Mon May 21 20:09:49 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -33,10 +33,10 @@ package fd_main_wbgen2_pkg is
tm_cycles_i : std_logic_vector(27 downto 0);
tdr_i : std_logic_vector(27 downto 0);
tdcsr_empty_i : std_logic;
calr_dmtd_tag_i : std_logic_vector(22 downto 0);
calr_dmtd_tag_rdy_i : std_logic;
spllr_tag_i : std_logic_vector(19 downto 0);
spllr_tag_rdy_i : std_logic;
dmtr_in_tag_i : std_logic_vector(30 downto 0);
dmtr_in_rdy_i : std_logic;
dmtr_out_tag_i : std_logic_vector(30 downto 0);
dmtr_out_rdy_i : std_logic;
iecraw_i : std_logic_vector(31 downto 0);
iectag_i : std_logic_vector(31 downto 0);
iepd_pdelay_i : std_logic_vector(7 downto 0);
......@@ -71,10 +71,10 @@ package fd_main_wbgen2_pkg is
tm_cycles_i => (others => '0'),
tdr_i => (others => '0'),
tdcsr_empty_i => '0',
calr_dmtd_tag_i => (others => '0'),
calr_dmtd_tag_rdy_i => '0',
spllr_tag_i => (others => '0'),
spllr_tag_rdy_i => '0',
dmtr_in_tag_i => (others => '0'),
dmtr_in_rdy_i => '0',
dmtr_out_tag_i => (others => '0'),
dmtr_out_rdy_i => '0',
iecraw_i => (others => '0'),
iectag_i => (others => '0'),
iepd_pdelay_i => (others => '0'),
......@@ -129,10 +129,6 @@ package fd_main_wbgen2_pkg is
calr_cal_pps_o : std_logic;
calr_cal_dmtd_o : std_logic;
calr_psel_o : std_logic_vector(3 downto 0);
calr_dmtd_fbsel_o : std_logic;
spllr_mode_o : std_logic;
sdacr_dac_val_o : std_logic_vector(15 downto 0);
sdacr_dac_val_wr_o : std_logic;
adsfr_o : std_logic_vector(17 downto 0);
atmcr_c_thr_o : std_logic_vector(3 downto 0);
atmcr_f_thr_o : std_logic_vector(22 downto 0);
......@@ -189,10 +185,6 @@ package fd_main_wbgen2_pkg is
calr_cal_pps_o => '0',
calr_cal_dmtd_o => '0',
calr_psel_o => (others => '0'),
calr_dmtd_fbsel_o => '0',
spllr_mode_o => '0',
sdacr_dac_val_o => (others => '0'),
sdacr_dac_val_wr_o => '0',
adsfr_o => (others => '0'),
atmcr_c_thr_o => (others => '0'),
atmcr_f_thr_o => (others => '0'),
......@@ -258,10 +250,10 @@ tmp.tm_secl_i := f_x_to_zero(left.tm_secl_i) or f_x_to_zero(right.tm_secl_i);
tmp.tm_cycles_i := f_x_to_zero(left.tm_cycles_i) or f_x_to_zero(right.tm_cycles_i);
tmp.tdr_i := f_x_to_zero(left.tdr_i) or f_x_to_zero(right.tdr_i);
tmp.tdcsr_empty_i := f_x_to_zero(left.tdcsr_empty_i) or f_x_to_zero(right.tdcsr_empty_i);
tmp.calr_dmtd_tag_i := f_x_to_zero(left.calr_dmtd_tag_i) or f_x_to_zero(right.calr_dmtd_tag_i);
tmp.calr_dmtd_tag_rdy_i := f_x_to_zero(left.calr_dmtd_tag_rdy_i) or f_x_to_zero(right.calr_dmtd_tag_rdy_i);
tmp.spllr_tag_i := f_x_to_zero(left.spllr_tag_i) or f_x_to_zero(right.spllr_tag_i);
tmp.spllr_tag_rdy_i := f_x_to_zero(left.spllr_tag_rdy_i) or f_x_to_zero(right.spllr_tag_rdy_i);
tmp.dmtr_in_tag_i := f_x_to_zero(left.dmtr_in_tag_i) or f_x_to_zero(right.dmtr_in_tag_i);
tmp.dmtr_in_rdy_i := f_x_to_zero(left.dmtr_in_rdy_i) or f_x_to_zero(right.dmtr_in_rdy_i);
tmp.dmtr_out_tag_i := f_x_to_zero(left.dmtr_out_tag_i) or f_x_to_zero(right.dmtr_out_tag_i);
tmp.dmtr_out_rdy_i := f_x_to_zero(left.dmtr_out_rdy_i) or f_x_to_zero(right.dmtr_out_rdy_i);
tmp.iecraw_i := f_x_to_zero(left.iecraw_i) or f_x_to_zero(right.iecraw_i);
tmp.iectag_i := f_x_to_zero(left.iectag_i) or f_x_to_zero(right.iectag_i);
tmp.iepd_pdelay_i := f_x_to_zero(left.iepd_pdelay_i) or f_x_to_zero(right.iepd_pdelay_i);
......
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ 4130caeb
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Mon May 21 20:09:49 2012
-- Created : Mon Jun 4 13:42:20 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -34,8 +34,8 @@ entity fd_main_wb_slave is
wb_int_o : out std_logic;
clk_ref_i : in std_logic;
tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic;
dmtr_in_rd_ack_o : out std_logic;
dmtr_out_rd_ack_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
......@@ -155,8 +155,6 @@ signal fd_main_calr_psel_swb_delay : std_logic ;
signal fd_main_calr_psel_swb_s0 : std_logic ;
signal fd_main_calr_psel_swb_s1 : std_logic ;
signal fd_main_calr_psel_swb_s2 : std_logic ;
signal fd_main_calr_dmtd_fbsel_int : std_logic ;
signal fd_main_spllr_mode_int : std_logic ;
signal fd_main_adsfr_int : std_logic_vector(17 downto 0);
signal fd_main_adsfr_swb : std_logic ;
signal fd_main_adsfr_swb_delay : std_logic ;
......@@ -331,11 +329,8 @@ begin
fd_main_calr_psel_int <= "0000";
fd_main_calr_psel_swb <= '0';
fd_main_calr_psel_swb_delay <= '0';
fd_main_calr_dmtd_fbsel_int <= '0';
calr_rd_ack_o <= '0';
spllr_rd_ack_o <= '0';
fd_main_spllr_mode_int <= '0';
regs_o.sdacr_dac_val_wr_o <= '0';
dmtr_in_rd_ack_o <= '0';
dmtr_out_rd_ack_o <= '0';
fd_main_adsfr_int <= "000000000000000000";
fd_main_adsfr_swb <= '0';
fd_main_adsfr_swb_delay <= '0';
......@@ -397,9 +392,8 @@ begin
regs_o.rstr_rst_core_wr_o <= '0';
regs_o.rstr_lock_wr_o <= '0';
tcr_rd_ack_o <= '0';
calr_rd_ack_o <= '0';
spllr_rd_ack_o <= '0';
regs_o.sdacr_dac_val_wr_o <= '0';
dmtr_in_rd_ack_o <= '0';
dmtr_out_rd_ack_o <= '0';
regs_o.scr_data_load_o <= '0';
fd_main_scr_start_int <= '0';
fd_main_tsbcr_purge_int <= '0';
......@@ -460,7 +454,6 @@ begin
fd_main_calr_cal_pulse_int_delay <= '0';
fd_main_calr_psel_swb <= fd_main_calr_psel_swb_delay;
fd_main_calr_psel_swb_delay <= '0';
regs_o.sdacr_dac_val_wr_o <= '0';
fd_main_adsfr_swb <= fd_main_adsfr_swb_delay;
fd_main_adsfr_swb_delay <= '0';
fd_main_atmcr_c_thr_swb <= fd_main_atmcr_c_thr_swb_delay;
......@@ -788,49 +781,11 @@ begin
fd_main_calr_psel_int <= wrdata_reg(6 downto 3);
fd_main_calr_psel_swb <= '1';
fd_main_calr_psel_swb_delay <= '1';
fd_main_calr_dmtd_fbsel_int <= wrdata_reg(7);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= fd_main_calr_cal_pps_int;
rddata_reg(2) <= fd_main_calr_cal_dmtd_int;
rddata_reg(6 downto 3) <= fd_main_calr_psel_int;
rddata_reg(7) <= fd_main_calr_dmtd_fbsel_int;
rddata_reg(30 downto 8) <= regs_i.calr_dmtd_tag_i;
calr_rd_ack_o <= '1';
rddata_reg(31) <= regs_i.calr_dmtd_tag_rdy_i;
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
fd_main_spllr_mode_int <= wrdata_reg(21);
end if;
rddata_reg(19 downto 0) <= regs_i.spllr_tag_i;
spllr_rd_ack_o <= '1';
rddata_reg(20) <= regs_i.spllr_tag_rdy_i;
rddata_reg(21) <= fd_main_spllr_mode_int;
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
regs_o.sdacr_dac_val_wr_o <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
......@@ -856,6 +811,22 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.dmtr_in_tag_i;
dmtr_in_rd_ack_o <= '1';
rddata_reg(31) <= regs_i.dmtr_in_rdy_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(30 downto 0) <= regs_i.dmtr_out_tag_i;
dmtr_out_rd_ack_o <= '1';
rddata_reg(31) <= regs_i.dmtr_out_rdy_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001100" =>
......@@ -1735,8 +1706,8 @@ begin
end process;
-- Triggers calibration pulses
-- synchronizer chain for field : Triggers calibration pulses (type RW/RO, clk_sys_i <-> clk_ref_i)
-- Produce DDMTD calibration pattern
-- synchronizer chain for field : Produce DDMTD calibration pattern (type RW/RO, clk_sys_i <-> clk_ref_i)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
......@@ -1771,17 +1742,10 @@ begin
end process;
-- DMTD Feedback Channel Select
regs_o.calr_dmtd_fbsel_o <= fd_main_calr_dmtd_fbsel_int;
-- DMTD Tag
-- DMTD Tag Ready
-- Frequency/Phase tag
-- Tag Ready
-- Freq/Phase mode select
regs_o.spllr_mode_o <= fd_main_spllr_mode_int;
-- DAC Value
-- pass-through field: DAC Value in register: Softpll DAC Register
regs_o.sdacr_dac_val_o <= wrdata_reg(15 downto 0);
-- DMTD Tag
-- DMTD Tag Ready
-- ADFSR Value
-- asynchronous std_logic_vector register : ADFSR Value (type RW/RO, clk_ref_i <-> clk_sys_i)
process (clk_ref_i, rst_n_i)
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ 4130caeb
......@@ -374,7 +374,6 @@ peripheral {
reg {
prefix = "CALR";
name = "Calibration register";
field {
clock = "clk_ref_i";
......@@ -397,8 +396,8 @@ peripheral {
};
field {
clock = "clk_ref_i";
name = "Triggers calibration pulses";
-- clock = "clk_ref_i";
name = "Produce DDMTD calibration pattern";
description = "write 1: Enables DMTD test pattern generation on Delay chain input and output selected in PSEL.\
write 0: DMTD pattern generation disabled.";
prefix = "CAL_DMTD";
......@@ -418,23 +417,18 @@ write 0: DMTD pattern generation disabled.";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
prefix = "DMTR_IN";
name = "DMTD Input Tag Register";
field {
name = "DMTD Feedback Channel Select";
prefix = "DMTD_FBSEL";
type = BIT;
description = "0: samples DDMTD pattern on the delay input\
1: samples DDMTD pattern on the delay output";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
ack_read = "calr_rd_ack_o";
ack_read = "dmtr_in_rd_ack_o";
name = "DMTD Tag";
prefix = "DMTD_TAG";
size = 23;
prefix = "TAG";
size = 31;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -442,64 +436,37 @@ write 0: DMTD pattern generation disabled.";
field {
name = "DMTD Tag Ready";
prefix = "DMTD_TAG_RDY";
prefix = "RDY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Softpll Register";
prefix = "SPLLR";
description = "Minimal SoftPLL register required to calibrate the card if it there's no WR core in the design";
reg {
prefix = "DMTR_OUT";
name = "DMTD Output Tag Register";
field {
ack_read = "spllr_rd_ack_o";
ack_read = "dmtr_out_rd_ack_o";
name = "Frequency/Phase tag";
name = "DMTD Tag";
prefix = "TAG";
size = 31;
type = SLV;
size = 20;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Tag Ready";
prefix = "TAG_RDY";
name = "DMTD Tag Ready";
prefix = "RDY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Freq/Phase mode select";
description = "0: sample frequency (pre-locking)\
1: sample phase";
prefix = "MODE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Softpll DAC Register";
prefix = "SDACR";
description = "DMTD Dac Control register, used for calibration when there's no associated WR core";
field {
name = "DAC Value";
prefix = "DAC_VAL";
type = PASS_THROUGH;
size = 16;
};
};
reg {
prefix = "ADSFR";
name = "Acam to Delay line fractional part Scale Factor Register";
......
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