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FMC DEL 1ns 4cha
Commit b2ff08f1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fd_wishbone_slave: added WR_READY flag

parent 9e5f27f9
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Showing with 39 additions and 11 deletions
hdl/rtl/fd_wishbone_slave.vhd
View file @ b2ff08f1
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Fine Delay WB -- Title : Wishbone slave core for Fine Delay Wishbone slave
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- File : fine_delay_wb.vhd -- File : fd_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fine_delay_wb.wb -- Author : auto-generated by wbgen2 from fd_wishbone_slave.wb
-- Created : Mon Aug 29 21:41:54 2011 -- Created : Wed Aug 31 11:09:47 2011
-- Standard : VHDL'87 -- Standard : VHDL'87
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fine_delay_wb.wb -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_wishbone_slave.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY! -- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
--------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------
...@@ -18,7 +18,7 @@ use work.wbgen2_pkg.all; ...@@ -18,7 +18,7 @@ use work.wbgen2_pkg.all;
use work.fd_wbgen2_pkg.all; use work.fd_wbgen2_pkg.all;
entity fine_delay_wb is entity fd_wishbone_slave is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
wb_clk_i : in std_logic; wb_clk_i : in std_logic;
...@@ -36,9 +36,9 @@ port ( ...@@ -36,9 +36,9 @@ port (
irq_ts_buf_notempty_i : in std_logic; irq_ts_buf_notempty_i : in std_logic;
regs_b : inout t_fd_registers regs_b : inout t_fd_registers
); );
end fine_delay_wb; end fd_wishbone_slave;
architecture syn of fine_delay_wb is architecture syn of fd_wishbone_slave is
signal fd_gcr_bypass_int : std_logic ; signal fd_gcr_bypass_int : std_logic ;
signal fd_gcr_bypass_sync0 : std_logic ; signal fd_gcr_bypass_sync0 : std_logic ;
...@@ -56,6 +56,8 @@ signal fd_gcr_csync_wr_int_delay : std_logic ; ...@@ -56,6 +56,8 @@ signal fd_gcr_csync_wr_int_delay : std_logic ;
signal fd_gcr_csync_wr_sync0 : std_logic ; signal fd_gcr_csync_wr_sync0 : std_logic ;
signal fd_gcr_csync_wr_sync1 : std_logic ; signal fd_gcr_csync_wr_sync1 : std_logic ;
signal fd_gcr_csync_wr_sync2 : std_logic ; signal fd_gcr_csync_wr_sync2 : std_logic ;
signal fd_gcr_wr_ready_sync0 : std_logic ;
signal fd_gcr_wr_ready_sync1 : std_logic ;
signal fd_tar_data_int_read : std_logic_vector(27 downto 0); signal fd_tar_data_int_read : std_logic_vector(27 downto 0);
signal fd_tar_data_int_write : std_logic_vector(27 downto 0); signal fd_tar_data_int_write : std_logic_vector(27 downto 0);
signal fd_tar_data_lw : std_logic ; signal fd_tar_data_lw : std_logic ;
...@@ -978,10 +980,11 @@ begin ...@@ -978,10 +980,11 @@ begin
fd_gcr_csync_int_int_delay <= wrdata_reg(2); fd_gcr_csync_int_int_delay <= wrdata_reg(2);
fd_gcr_csync_wr_int <= wrdata_reg(3); fd_gcr_csync_wr_int <= wrdata_reg(3);
fd_gcr_csync_wr_int_delay <= wrdata_reg(3); fd_gcr_csync_wr_int_delay <= wrdata_reg(3);
rddata_reg(4) <= 'X';
else else
rddata_reg(0) <= fd_gcr_bypass_int; rddata_reg(0) <= fd_gcr_bypass_int;
rddata_reg(1) <= fd_gcr_input_en_int; rddata_reg(1) <= fd_gcr_input_en_int;
rddata_reg(4) <= 'X'; rddata_reg(4) <= fd_gcr_wr_ready_sync1;
rddata_reg(5) <= 'X'; rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X'; rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X'; rddata_reg(7) <= 'X';
...@@ -2467,6 +2470,20 @@ begin ...@@ -2467,6 +2470,20 @@ begin
end process; end process;
-- White Rabbit Timecode Ready
-- synchronizer chain for field : White Rabbit Timecode Ready (type RO/WO, clk_ref_i -> bus_clock_int)
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_gcr_wr_ready_sync0 <= '0';
fd_gcr_wr_ready_sync1 <= '0';
elsif rising_edge(clk_ref_i) then
fd_gcr_wr_ready_sync0 <= regs_b.gcr_wr_ready_i;
fd_gcr_wr_ready_sync1 <= fd_gcr_wr_ready_sync0;
end if;
end process;
-- DATA -- DATA
-- asynchronous std_logic_vector register : DATA (type RW/WO, clk_ref_i <-> bus_clock_int) -- asynchronous std_logic_vector register : DATA (type RW/WO, clk_ref_i <-> bus_clock_int)
process (clk_ref_i, rst_n_i) process (clk_ref_i, rst_n_i)
......
hdl/rtl/fd_wishbone_slave.wb
View file @ b2ff08f1
-- -*- Mode: LUA; tab-width: 2 -*- -- -*- Mode: LUA; tab-width: 2 -*-
peripheral { peripheral {
name = "Fine Delay WB"; name = "Fine Delay Wishbone slave";
hdl_entity = "fine_delay_wb"; hdl_entity = "fd_wishbone_slave";
prefix = "fd"; prefix = "fd";
...@@ -62,6 +62,17 @@ peripheral { ...@@ -62,6 +62,17 @@ peripheral {
type = MONOSTABLE; type = MONOSTABLE;
clock = "clk_ref_i"; clock = "clk_ref_i";
}; };
field {
name = "White Rabbit Timecode Ready";
description = "read 1: time code provided to the external input from White Rabbit Core is valid. Can proceed with counter sync.\
read 0: WR time code input is invalid. Can't do sounter sync for the moment.";
prefix = "WR_READY";
type = BIT;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
}; };
reg { reg {
......
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