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FMC DEL 1ns 4cha
Commit b2fa4dd4 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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rtl/fd_main_wishbone_slave: added raw TS readout, TSBR_DEBUG and TSBR_ADVANCE registers

parent 55c507d1
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hdl/rtl/fd_main_wbgen2_pkg.vhd
View file @ b2fa4dd4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:21 2012
-- Created : Mon May 21 20:09:49 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -55,6 +55,7 @@ package fd_main_wbgen2_pkg is
i2cr_scl_in_i : std_logic;
i2cr_sda_in_i : std_logic;
tder1_vcxo_freq_i : std_logic_vector(31 downto 0);
tsbr_debug_i : std_logic_vector(31 downto 0);
end record;
constant c_fd_main_in_registers_init_value: t_fd_main_in_registers := (
......@@ -91,7 +92,8 @@ package fd_main_wbgen2_pkg is
tsbr_fid_seqid_i => (others => '0'),
i2cr_scl_in_i => '0',
i2cr_sda_in_i => '0',
tder1_vcxo_freq_i => (others => '0')
tder1_vcxo_freq_i => (others => '0'),
tsbr_debug_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -147,11 +149,13 @@ package fd_main_wbgen2_pkg is
tsbcr_enable_o : std_logic;
tsbcr_purge_o : std_logic;
tsbcr_rst_seq_o : std_logic;
tsbcr_raw_o : std_logic;
tsbir_timeout_o : std_logic_vector(9 downto 0);
tsbir_threshold_o : std_logic_vector(11 downto 0);
i2cr_scl_out_o : std_logic;
i2cr_sda_out_o : std_logic;
tder2_pelt_drive_o : std_logic_vector(31 downto 0);
tsbr_advance_adv_o : std_logic;
end record;
constant c_fd_main_out_registers_init_value: t_fd_main_out_registers := (
......@@ -205,11 +209,13 @@ package fd_main_wbgen2_pkg is
tsbcr_enable_o => '0',
tsbcr_purge_o => '0',
tsbcr_rst_seq_o => '0',
tsbcr_raw_o => '0',
tsbir_timeout_o => (others => '0'),
tsbir_threshold_o => (others => '0'),
i2cr_scl_out_o => '0',
i2cr_sda_out_o => '0',
tder2_pelt_drive_o => (others => '0')
tder2_pelt_drive_o => (others => '0'),
tsbr_advance_adv_o => '0'
);
function "or" (left, right: t_fd_main_in_registers) return t_fd_main_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......@@ -274,6 +280,7 @@ tmp.tsbr_fid_seqid_i := f_x_to_zero(left.tsbr_fid_seqid_i) or f_x_to_zero(right.
tmp.i2cr_scl_in_i := f_x_to_zero(left.i2cr_scl_in_i) or f_x_to_zero(right.i2cr_scl_in_i);
tmp.i2cr_sda_in_i := f_x_to_zero(left.i2cr_sda_in_i) or f_x_to_zero(right.i2cr_sda_in_i);
tmp.tder1_vcxo_freq_i := f_x_to_zero(left.tder1_vcxo_freq_i) or f_x_to_zero(right.tder1_vcxo_freq_i);
tmp.tsbr_debug_i := f_x_to_zero(left.tsbr_debug_i) or f_x_to_zero(right.tsbr_debug_i);
return tmp;
end function;
end package body;
hdl/rtl/fd_main_wishbone_slave.vhd
View file @ b2fa4dd4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_main_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
-- Created : Wed Apr 11 11:05:21 2012
-- Created : Mon May 21 20:09:49 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -36,7 +36,8 @@ entity fd_main_wb_slave is
tcr_rd_ack_o : out std_logic;
calr_rd_ack_o : out std_logic;
spllr_rd_ack_o : out std_logic;
advance_rbuf_o : out std_logic;
tsbcr_read_ack_o : out std_logic;
fid_read_ack_o : out std_logic;
irq_ts_buf_notempty_i : in std_logic;
irq_dmtd_spll_i : in std_logic;
irq_sync_status_i : in std_logic;
......@@ -233,11 +234,14 @@ signal fd_main_tsbcr_rst_seq_int_delay : std_logic ;
signal fd_main_tsbcr_rst_seq_sync0 : std_logic ;
signal fd_main_tsbcr_rst_seq_sync1 : std_logic ;
signal fd_main_tsbcr_rst_seq_sync2 : std_logic ;
signal fd_main_tsbcr_raw_int : std_logic ;
signal fd_main_tsbir_timeout_int : std_logic_vector(9 downto 0);
signal fd_main_tsbir_threshold_int : std_logic_vector(11 downto 0);
signal fd_main_i2cr_scl_out_int : std_logic ;
signal fd_main_i2cr_sda_out_int : std_logic ;
signal fd_main_tder2_pelt_drive_int : std_logic_vector(31 downto 0);
signal fd_main_tsbr_advance_adv_dly0 : std_logic ;
signal fd_main_tsbr_advance_adv_int : std_logic ;
signal eic_idr_int : std_logic_vector(2 downto 0);
signal eic_idr_write_int : std_logic ;
signal eic_ier_int : std_logic_vector(2 downto 0);
......@@ -371,12 +375,15 @@ begin
fd_main_tsbcr_purge_int <= '0';
fd_main_tsbcr_rst_seq_int <= '0';
fd_main_tsbcr_rst_seq_int_delay <= '0';
tsbcr_read_ack_o <= '0';
fd_main_tsbcr_raw_int <= '0';
fd_main_tsbir_timeout_int <= "0000000000";
fd_main_tsbir_threshold_int <= "000000000000";
advance_rbuf_o <= '0';
fid_read_ack_o <= '0';
fd_main_i2cr_scl_out_int <= '0';
fd_main_i2cr_sda_out_int <= '0';
fd_main_tder2_pelt_drive_int <= "00000000000000000000000000000000";
fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -396,7 +403,9 @@ begin
regs_o.scr_data_load_o <= '0';
fd_main_scr_start_int <= '0';
fd_main_tsbcr_purge_int <= '0';
advance_rbuf_o <= '0';
tsbcr_read_ack_o <= '0';
fid_read_ack_o <= '0';
fd_main_tsbr_advance_adv_int <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
......@@ -1003,6 +1012,7 @@ begin
fd_main_tsbcr_purge_int <= wrdata_reg(6);
fd_main_tsbcr_rst_seq_int <= wrdata_reg(7);
fd_main_tsbcr_rst_seq_int_delay <= wrdata_reg(7);
fd_main_tsbcr_raw_int <= wrdata_reg(22);
end if;
rddata_reg(4 downto 0) <= fd_main_tsbcr_chan_mask_int;
rddata_reg(5) <= fd_main_tsbcr_enable_int;
......@@ -1010,8 +1020,9 @@ begin
rddata_reg(7) <= 'X';
rddata_reg(8) <= regs_i.tsbcr_full_i;
rddata_reg(9) <= regs_i.tsbcr_empty_i;
tsbcr_read_ack_o <= '1';
rddata_reg(21 downto 10) <= regs_i.tsbcr_count_i;
rddata_reg(22) <= 'X';
rddata_reg(22) <= fd_main_tsbcr_raw_int;
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
......@@ -1094,7 +1105,7 @@ begin
rddata_reg(3 downto 0) <= regs_i.tsbr_fid_channel_i;
rddata_reg(15 downto 4) <= regs_i.tsbr_fid_fine_i;
rddata_reg(31 downto 16) <= regs_i.tsbr_fid_seqid_i;
advance_rbuf_o <= '1';
fid_read_ack_o <= '1';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011010" =>
......@@ -1149,6 +1160,51 @@ begin
rddata_reg(31 downto 0) <= fd_main_tder2_pelt_drive_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tsbr_debug_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011110" =>
if (wb_we_i = '1') then
fd_main_tsbr_advance_adv_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "100000" =>
if (wb_we_i = '1') then
eic_idr_write_int <= '1';
......@@ -1982,6 +2038,8 @@ begin
-- Buffer full
-- Buffer empty
-- Buffer entries count
-- RAW readout mode enable
regs_o.tsbcr_raw_o <= fd_main_tsbcr_raw_int;
-- IRQ timeout [milliseconds]
regs_o.tsbir_timeout_o <= fd_main_tsbir_timeout_int;
-- Interrupt threshold
......@@ -2001,6 +2059,20 @@ begin
-- VCXO Frequency
-- Peltier PWM drive
regs_o.tder2_pelt_drive_o <= fd_main_tder2_pelt_drive_int;
-- Debug value
-- Advance buffer readout
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
fd_main_tsbr_advance_adv_dly0 <= '0';
regs_o.tsbr_advance_adv_o <= '0';
elsif rising_edge(clk_sys_i) then
fd_main_tsbr_advance_adv_dly0 <= fd_main_tsbr_advance_adv_int;
regs_o.tsbr_advance_adv_o <= fd_main_tsbr_advance_adv_int and (not fd_main_tsbr_advance_adv_dly0);
end if;
end process;
-- extra code for reg/fifo/mem: Interrupt disable register
eic_idr_int(2 downto 0) <= wrdata_reg(2 downto 0);
-- extra code for reg/fifo/mem: Interrupt enable register
......
hdl/rtl/fd_main_wishbone_slave.wb
View file @ b2fa4dd4
......@@ -753,7 +753,9 @@ write 0: DMTD pattern generation disabled.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tsbcr_read_ack_o";
};
field {
name = "Buffer entries count";
prefix = "COUNT";
......@@ -762,6 +764,14 @@ write 0: DMTD pattern generation disabled.";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RAW readout mode enable";
prefix = "RAW";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......@@ -861,7 +871,7 @@ write 0: DMTD pattern generation disabled.";
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "advance_rbuf_o";
ack_read = "fid_read_ack_o";
};
};
......@@ -927,6 +937,32 @@ write 0: DMTD pattern generation disabled.";
};
};
reg {
name = "Timestamp Buffer Debug Values Register";
prefix = "TSBR_DEBUG";
field {
name = "Debug value";
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Timestamp Buffer Advance Register";
prefix = "TSBR_ADVANCE";
field {
name = "Advance buffer readout";
descriptor = "write 1: transfer the latest sample from the ring buffer to TSBR_SEC/CYCLES/FID registers,\
write 0: no effect";
type = MONOSTABLE;
prefix = "ADV";
};
};
irq {
name = "TS Buffer not empty.";
......
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