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FMC DEL 1ns 4cha
Commit 55c507d1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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merged software changes

parents e8824c55 2d9c8d9c
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Showing with 262 additions and 148 deletions
software/include/fd_channel_regs.h
View file @ 55c507d1
......@@ -3,7 +3,7 @@
* File : fd_channel_regs.h
* Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
* Created : Wed Feb 29 12:04:02 2012
* Created : Wed Apr 11 11:05:22 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......
software/include/fd_main_regs.h
View file @ 55c507d1
......@@ -3,7 +3,7 @@
* File : fd_main_regs.h
* Author : auto-generated by wbgen2 from fd_main_wishbone_slave.wb
* Created : Wed Feb 29 12:04:02 2012
* Created : Wed Apr 11 11:05:22 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_main_wishbone_slave.wb
......@@ -64,6 +64,9 @@
/* definitions for field: PLL Locked in reg: Global Control Register */
#define FD_GCR_DDR_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Mezzanice Present in reg: Global Control Register */
#define FD_GCR_FMC_PRESENT WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Timing Control Register */
/* definitions for field: DMTD Clock Status in reg: Timing Control Register */
......@@ -325,17 +328,21 @@
/* definitions for field: SDA Line in in reg: I2C bitbanged IO register */
#define FD_I2CR_SDA_IN WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Debug in in reg: I2C bitbanged IO register */
#define FD_I2CR_DBG_MASK WBGEN2_GEN_MASK(4, 4)
#define FD_I2CR_DBG_SHIFT 4
#define FD_I2CR_DBG_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define FD_I2CR_DBG_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for register: Test/Debug register 1 */
/* definitions for field: VCXO Frequency in reg: Test/Debug register 1 */
#define FD_TDER1_VCXO_FREQ_MASK WBGEN2_GEN_MASK(0, 32)
#define FD_TDER1_VCXO_FREQ_SHIFT 0
#define FD_TDER1_VCXO_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FD_TDER1_VCXO_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Test/Debug register 1 */
/* definitions for field: Debug out in reg: I2C bitbanged IO register */
#define FD_I2CR_DBGOUT_MASK WBGEN2_GEN_MASK(8, 12)
#define FD_I2CR_DBGOUT_SHIFT 8
#define FD_I2CR_DBGOUT_W(value) WBGEN2_GEN_WRITE(value, 8, 12)
#define FD_I2CR_DBGOUT_R(reg) WBGEN2_GEN_READ(reg, 8, 12)
/* definitions for field: Peltier PWM drive in reg: Test/Debug register 1 */
#define FD_TDER2_PELT_DRIVE_MASK WBGEN2_GEN_MASK(0, 32)
#define FD_TDER2_PELT_DRIVE_SHIFT 0
#define FD_TDER2_PELT_DRIVE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FD_TDER2_PELT_DRIVE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Interrupt disable register */
......@@ -434,6 +441,10 @@
#define FD_REG_TSBR_FID 0x00000064
/* [0x68]: REG I2C bitbanged IO register */
#define FD_REG_I2CR 0x00000068
/* [0x6c]: REG Test/Debug register 1 */
#define FD_REG_TDER1 0x0000006c
/* [0x70]: REG Test/Debug register 1 */
#define FD_REG_TDER2 0x00000070
/* [0x80]: REG Interrupt disable register */
#define FD_REG_EIC_IDR 0x00000080
/* [0x84]: REG Interrupt enable register */
......
software/include/fdelay_private.h
View file @ 55c507d1
......@@ -16,6 +16,8 @@
#include <stdint.h>
/* SPI Bus chip selects */
#define CS_DAC 0 /* AD9516 PLL */
#define CS_PLL 1 /* AD9516 PLL */
#define CS_GPIO 2 /* MCP23S17 GPIO */
......
software/include/rr_io.h
View file @ 55c507d1
......@@ -4,6 +4,7 @@
#include <stdint.h>
#include <rawrabbit.h>
int rr_bind(int a_fd);
int rr_init(int bus, int devfn);
int rr_writel(uint32_t data, uint32_t addr);
uint32_t rr_readl(uint32_t addr);
......
software/lib/Makefile
View file @ 55c507d1
CFLAGS = -I../include -g -Imini_bone -Ispll -DPERFORM_LONG_TESTS
CFLAGS = -I../include -g -Imini_bone -Ispll
OBJS_LIB = fdelay_lib.o rr_io.o i2c_master.o onewire.o mini_bone/minibone_lib.o mini_bone/ptpd_netif.o spec_common.o
#uncomment for extra tests (DAC, output stage INL/DNL)
#CFLAGS += -DPERFORM_LONG_TESTS
all: testprog lib testprog2 testprog3 testprog4
OBJS_LIB = fdelay_lib.o fdelay_bus.o rr_io.o i2c_master.o onewire.o mini_bone/minibone_lib.o mini_bone/ptpd_netif.o spec_common.o
all: testprog lib testprog3 testprog4
lib: $(OBJS_LIB)
gcc -shared -o libfinedelay.so $(OBJS_LIB)
......@@ -10,8 +13,8 @@ lib: $(OBJS_LIB)
testprog: lib fdelay_test.o
gcc -o fdelay_test $(OBJS_LIB) fdelay_test.o -lm
testprog2: lib fdelay_cal.o
gcc -o fdelay_cal $(OBJS_LIB) fdelay_cal.o -lm
#testprog2: lib fdelay_cal.o
# gcc -o fdelay_cal $(OBJS_LIB) fdelay_cal.o -lm
testprog3: lib fdelay_pps_demo.o
gcc -o fdelay_pps_demo $(OBJS_LIB) fdelay_pps_demo.o -lm
......
software/lib/fdelay_bus.c
View file @ 55c507d1
......@@ -36,10 +36,10 @@ uint32_t d = mbn_readl(priv, addr >> 2);
return d;
}
fdelay_device_t *fdelay_create_rawrabbit(uint32_t base_addr)
fdelay_device_t *fdelay_create_rawrabbit(int fd, uint32_t base_addr)
{
fdelay_device_t *dev = malloc(sizeof(fdelay_device_t));
rr_init(RR_DEVSEL_NONE, RR_DEVSEL_NONE);
rr_bind(fd);
dev->writel = my_rr_writel;
dev->readl = my_rr_readl;
dev->base_addr = base_addr;
......@@ -68,3 +68,14 @@ fdelay_device_t *fdelay_create_minibone(char *iface, char *mac_addr, uint32_t ba
return dev;
}
int fdelay_load_firmware(const char *path)
{
fprintf(stderr,"Booting up the FPGA with %s.\n", path);
if(rr_load_bitstream_from_file(path) < 0)
{
fprintf(stderr,"Failed to load FPGA bitstream.\n");
return -1;
}
return 0;
}
\ No newline at end of file
software/lib/fdelay_cal.c
View file @ 55c507d1
......@@ -71,7 +71,7 @@ main()
{
fdelay_device_t *dev = malloc(sizeof(fdelay_device_t));
rr_init();
rr_init(RR_DEVSEL_UNUSED, RR_DEVSEL_UNUSED);
dev->writel = my_writel;
dev->readl = my_readl;
......
software/lib/fdelay_lib.c
View file @ 55c507d1
......@@ -146,6 +146,8 @@ static void oc_spi_txrx(fdelay_device_t *dev, int ss, int num_bits, uint32_t in,
scr |= FD_SCR_SEL_PLL;
else if(ss == CS_GPIO)
scr |= FD_SCR_SEL_GPIO;
else if(ss == CS_DAC)
scr |= FD_SCR_SEL_DAC;
fd_writel(scr, FD_REG_SCR);
fd_writel(scr | FD_SCR_START, FD_REG_SCR);
......@@ -229,6 +231,38 @@ static int ad9516_init(fdelay_device_t *dev)
return 0;
}
static int test_pll_dac(fdelay_device_t *dev)
{
fd_decl_private(dev);
int f_hi, f_lo;
double range;
int i=0;
dbg("Testing DAC/VCXO... ");
oc_spi_txrx(dev, CS_DAC, 24, 0, NULL); /* Drive the DAC to 0 */
udelay(1000000);
f_lo = fd_readl(FD_REG_TDER1) & 0x7fffffff;
oc_spi_txrx(dev, CS_DAC, 24, 0xffff, NULL); /* Drive the DAC to +Vref */
udelay(1000000);
f_hi = fd_readl(FD_REG_TDER1) & 0x7fffffff;
range = (double)abs(f_hi - f_lo) / (double)f_lo * 1e6;
dbg("tuning range: %.1f ppm.\n", range);
if(range < 10.1)
{
fail(TEST_SPI, "Too little VCXO tuning range. Either a broken VCXO or (more likely) broken SPI connection to the DAC.");
return -1;
}
return 0;
}
/*
----------------------------
MCP23S17 SPI I/O Port Driver
......@@ -627,11 +661,12 @@ static void measure_linearity(double *x, int n, double *inl, double *dnl)
its linearity, performing an indirect check of the delay lines' and TDC signal connections. */
#define MAX_DNL 20
#define MAX_INL 50
#define MAX_INL 60
static int test_delay_transfer_function(fdelay_device_t *dev)
{
double inl, dnl;
int lin_fail = 0;
fd_decl_private(dev)
......@@ -659,15 +694,18 @@ static int test_delay_transfer_function(fdelay_device_t *dev)
dbg("Linearity: INL = %.1f ps, DNL = %.1f ps\n", inl, dnl);
if(inl > MAX_INL || dnl > MAX_DNL)
{
dbg("Linearity check failed.\n");
fail(TEST_DELAY_LINE, "Maximum INL/DNL exceeded, indicating a wrong connection of the delay chip and/or the TDC calibration signals");
return -1;
}
lin_fail=1;
}
if(lin_fail)
{
dbg("Linearity check failed.\n");
fail(TEST_DELAY_LINE, "Maximum INL/DNL exceeded, indicating a wrong connection of the delay chip and/or the TDC calibration signals");
return -1;
}
return 0;
/* FILE *f=fopen("t_func.dat","w");
......@@ -847,6 +885,14 @@ int fdelay_init(fdelay_device_t *dev)
return -1;
}
if(! (fd_readl(FD_REG_GCR) & FD_GCR_FMC_PRESENT))
{
fail(TEST_PRESENCE, "FMC Card not detected in the slot. Maybe a fault on PRSNT_L line?");
dbg("%s: FMC Presence line not active. Is the FMC correctly inserted into the carrier?\n", __FUNCTION__);
return -1;
}
rv = read_calibration_eeprom(dev, &hw->calib);
if(rv < 0)
......@@ -881,6 +927,8 @@ int fdelay_init(fdelay_device_t *dev)
if(ad9516_init(dev) < 0)
return -1;
if(ds18x_init(dev) < 0)
{
fail(TEST_SPI, "DS18x sensor not detected.");
......@@ -918,6 +966,12 @@ int fdelay_init(fdelay_device_t *dev)
initialization and calibration */
fd_writel( FD_GCR_BYPASS, FD_REG_GCR);
#ifdef PERFORM_LONG_TESTS
if(test_pll_dac(dev) < 0)
return -1;
#endif
/* Test if ACAM addr/data lines are OK */
if(acam_test_bus(dev) < 0)
return -1;
......@@ -932,6 +986,9 @@ int fdelay_init(fdelay_device_t *dev)
/* Switch the ACAM to be driven by the delay core instead of the host */
fd_writel( 0, FD_REG_GCR);
/* Disable external synchronization (i.e. WR) */
fd_writel( 0, FD_REG_TCR);
/* Clear and disable the timestamp readout buffer */
fd_writel( FD_TSBCR_PURGE | FD_TSBCR_RST_SEQ, FD_REG_TSBCR);
......@@ -1048,8 +1105,11 @@ int64_t fdelay_to_picos(const fdelay_time_t t)
static int poll_rbuf(fdelay_device_t *dev)
{
fd_decl_private(dev)
uint32_t tsbcr = fd_readl(FD_REG_TSBCR);
// fprintf(stderr,"Count %d empty %d\n", FD_TSBCR_COUNT_R(tsbcr), tsbcr & FD_TSBCR_EMPTY ? 1 : 0);
if((fd_readl(FD_REG_TSBCR) & FD_TSBCR_EMPTY) == 0)
if((tsbcr & FD_TSBCR_EMPTY) == 0)
return 1;
return 0;
}
......@@ -1116,10 +1176,11 @@ int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64
delay_ps -= hw->calib.zero_offset[channel-1];
start = fdelay_from_picos(delay_ps);
end = fdelay_from_picos(delay_ps + width_ps);
end = fdelay_from_picos(delay_ps + width_ps - 4000);
delta = fdelay_from_picos(delta_ps);
// printf("Start: %lld: %d:%d\n", start.utc, start.coarse, start.frac);
printf("Start: %lld: %d:%d rep %d\n", start.utc, start.coarse, start.frac, rep_count);
chan_writel(hw->frr_cur[channel-1], FD_REG_FRR);
......@@ -1137,7 +1198,7 @@ int fdelay_configure_output(fdelay_device_t *dev, int channel, int enable, int64
chan_writel(delta.frac, FD_REG_F_DELTA);
// chan_writel(0, FD_REG_RCR);
chan_writel(FD_RCR_REP_CNT_W(rep_count) | (rep_count < 0 ? FD_RCR_CONT : 0), FD_REG_RCR);
chan_writel(FD_RCR_REP_CNT_W(rep_count-1) | (rep_count < 0 ? FD_RCR_CONT : 0), FD_REG_RCR);
dcr = 0;
......@@ -1168,11 +1229,17 @@ int fdelay_configure_pulse_gen(fdelay_device_t *dev, int channel, int enable, fd
if(channel < 1 || channel > 4)
return -1;
start = t_start;
end = ts_add(start, fdelay_from_picos(width_ps));
delta = fdelay_from_picos(delta_ps);
end = fdelay_from_picos(fdelay_to_picos(start) + width_ps - 4000);
delta = fdelay_from_picos(delta_ps);
//start = t_start;
//end = ts_add(start, fdelay_from_picos(width_ps));
//delta = fdelay_from_picos(delta_ps);
// printf("Start: %lld: %d:%d\n", start.utc, start.coarse, start.frac);
//printf("Start: %lld: %d:%d\n", start.utc, start.coarse, start.frac);
//printf("width: %lld delta: %lld rep: %d\n", width_ps, delta_ps, rep_count);
chan_writel(hw->frr_cur[channel-1], FD_REG_FRR);
......@@ -1247,8 +1314,6 @@ int fdelay_get_time(fdelay_device_t *dev, fdelay_time_t *t)
return 0;
}
#if 0
/* To be rewritten to use interrupts and new WR FSM (see TCR register description).
Use the API provided in fdelay_lib.h */
......@@ -1259,59 +1324,30 @@ int fdelay_configure_sync(fdelay_device_t *dev, int mode)
if(mode == FDELAY_SYNC_LOCAL)
{
fd_writel(0, FD_REG_GCR);
// fd_writel(FD_GCR_CSYNC_INT, FD_REG_GCR);
fd_writel(0, FD_REG_TCR);
hw->wr_enabled = 0;
} else {
fd_writel(0, FD_REG_GCR);
fd_writel(FD_TCR_WR_ENABLE, FD_REG_TCR);
hw->wr_enabled = 1;
hw->wr_state = FDELAY_WR_OFFLINE;
}
}
int fdelay_get_sync_status(fdelay_device_t *dev)
{
int fdelay_check_sync(fdelay_device_t *dev)
{
fd_decl_private(dev)
if(!hw->wr_enabled) return FDELAY_FREE_RUNNING;
switch(hw->wr_state)
{
case FDELAY_WR_OFFLINE:
if(fd_readl(FD_REG_GCR) & FD_GCR_WR_READY)
{
dbg("-> WR Core synced\n");
hw->wr_state = FDELAY_WR_READY;
}
break;
case FDELAY_WR_READY:
fd_writel(FD_GCR_WR_LOCK_EN, FD_REG_GCR);
hw->wr_state = FDELAY_WR_SYNCING;
break;
case FDELAY_WR_SYNCING:
if(fd_readl(FD_REG_GCR) & FD_GCR_WR_LOCKED)
{
fd_writel(FD_GCR_WR_LOCK_EN | FD_GCR_CSYNC_WR, FD_REG_GCR);
fd_writel(FD_GCR_WR_LOCK_EN , FD_REG_GCR);
fd_writel(FD_GCR_WR_LOCK_EN | FD_GCR_INPUT_EN, FD_REG_GCR);
hw->wr_state = FDELAY_WR_SYNCED;
}
break;
case FDELAY_WR_SYNCED:
if((fd_readl(FD_REG_GCR) & FD_GCR_WR_LOCKED) == 0)
hw->wr_state = FDELAY_WR_OFFLINE;
break;
}
fprintf(stderr, "TCR %x\n", fd_readl(FD_REG_TCR) & FD_TCR_WR_LOCKED);
return hw->wr_state;
if(hw->wr_enabled && (fd_readl(FD_REG_TCR) & FD_TCR_WR_LOCKED))
return 1;
else if (!hw->wr_enabled)
return 1;
return 0;
}
#endif
# if 0
/* We might implement SPLL-based DMTD calibration, but not now - don't include in the driver */
......
software/lib/fdelay_test.c
View file @ 55c507d1
......@@ -3,54 +3,68 @@
#include "fdelay_lib.h"
#include "rr_io.h"
int spec_fdelay_init(int argc, char *argv[], fdelay_device_t *dev);
extern int spec_fdelay_init(int argc, char *argv[], fdelay_device_t *dev);
main(int argc, char *argv[])
{
fdelay_device_t dev;
fdelay_time_t t_cur, t_start;
fdelay_time_t t;
/* Initialize the fine delay generator */
if(spec_fdelay_init(argc, argv, &dev) < 0)
{
fdelay_show_test_results();
return -1;
}
fdelay_configure_trigger(&dev, 1,1);
/* Enable trigger input and 50 ohm termination */
/* Enable all outputs and set them to 500 ns delay, 100 ns pulse width, single output pulse per trigger */
fdelay_configure_output(&dev,1,1,500000, 100000, 100000, 0);
fdelay_configure_output(&dev,2,1,500000, 100000, 100000, 0);
fdelay_configure_output(&dev,3,1,500000, 100000, 100000, 0);
fdelay_configure_output(&dev,4,1,500000, 100000, 100000, 0);
/* fdelay_configure_output(&dev,1,1,500000, 100000, 100000, 1);
fdelay_configure_output(&dev,2,1,500000, 100000, 100000, 1);
fdelay_configure_output(&dev,3,1,500000, 100000, 100000, 1);
fdelay_configure_output(&dev,4,1,500000, 100000, 100000, 1);*/
t.utc = 0;
t.coarse = 0;
fdelay_set_time(&dev, t);
fdelay_configure_readout(&dev, 1);
// fd_update_spll(&dev);
int64_t prev = 0, dp, pmin=10000000000LL,pmax=0;
fdelay_configure_sync(&dev, FDELAY_SYNC_WR);
fprintf(stderr, "Syncing with WR Timebase...\n");
while(!fdelay_check_sync(&dev))
fprintf(stderr, ".");
fprintf(stderr, " locked!\n");
#if 0
fdelay_configure_trigger(&dev, 1, 0);
fdelay_configure_readout(&dev, 1);//int enable)
int seq_prev = 0;
int64_t t_prev = 0;
#if 1
for(;;)
{
fdelay_time_t ts;
if(fdelay_read(&dev, &ts, 1) == 1)
{
int64_t ts_p = fdelay_to_picos(ts), d;
d=ts_p - prev;
if(prev > 0)
{
if(d<pmin) pmin=d;
if(d>pmax) pmax=d;
fprintf(stderr,"Got it %lld:%d:%d delta %lld span %lld\n", ts.utc, ts.coarse, ts.frac, d, pmax-pmin);
}
prev = ts_p;
}
}
#endif
for(;;)
{
fdelay_update_calibration(&dev);
sleep(1);
}
{
fdelay_time_t ts;
int64_t ts_i;
if(fdelay_read(&dev, &ts, 1) == 1)
{
ts_i = fdelay_to_picos(ts);
fprintf(stderr,"ts = %-20lld ps, delta = %-20lld, seq = %-6d seq_delta=%-6d\n",
ts_i, ts_i-t_prev, ts.seq_id, ts.seq_id-seq_prev);
seq_prev = ts.seq_id;
t_prev= ts_i;
}
}
#endif
// fdelay_
for(;;)
{
}
}
software/lib/rr_io.c
View file @ 55c507d1
......@@ -18,6 +18,12 @@
static int fd;
int rr_bind(int a_fd)
{
fd = a_fd;
return 0;
}
int rr_init(int bus, int devfn)
{
struct rr_devsel devsel;
......
software/lib/spec_common.c
View file @ 55c507d1
......@@ -50,13 +50,13 @@ int spec_fdelay_init(int argc, char *argv[], fdelay_device_t *dev)
dev->writel = spec_writel;
dev->readl = spec_readl;
dev->base_addr = 0x84000;
dev->base_addr = 0x80000;
if(rr_load_bitstream_from_file(fw_name) < 0)
/* if(rr_load_bitstream_from_file(fw_name) < 0)
{
fprintf(stderr,"Failed to load FPGA bitstream.\n");
return -1;
}
}*/
if(fdelay_init(dev) < 0)
return -1;
......
software/python/demo.py
View file @ 55c507d1
......@@ -68,16 +68,25 @@ def on_chk_wr():
if __name__ == "__main__":
import os,sys
if(os.getuid() != 0):
print("Sorry, I must be run as root...");
sys.exit(-1)
fd = os.open("/dev/rawrabbit", os.O_SYNC)
if(fd < 0):
print("Can't open the rawrabbit device. Is the rawrabbit driver installed?")
sys.exit(-1)
card = FineDelay(fd)
app = QApplication(sys.argv)
if(sys.argv[1] == "1"):
location = "minibone/eth0/00:50:0c:de:bc:f8/0x100000"
else:
location = "minibone/eth0/00:50:e4:95:36:f8/0x100000"
m = MainWindow()
m.show()
m.setWindowTitle("Fine Delay Demo @ %s" % location)
card = FineDelay(location)
import os
m.setWindowTitle("Fine Delay Demo")
m.wr_status.setText("")
ch_enable = [m.en_ch1, m.en_ch2, m.en_ch3, m.en_ch4];
ch_nsec = [m.nsec_ch1, m.nsec_ch2, m.nsec_ch3, m.nsec_ch4];
......
software/python/fdelay_lib.py
View file @ 55c507d1
......@@ -3,12 +3,14 @@
from ctypes import *
import sys
import re
import os
class fd_timestamp(Structure):
_fields_ = [("utc", c_ulong),
("coarse", c_ulong),
("frac", c_ulong),
("seq_id", c_ushort)]
_fields_ = [("utc", c_ulonglong),
("coarse", c_ulong),
("frac", c_ulong),
("seq_id", c_ushort),
("channel", c_int)]
def nsecs(self):
return (float(self.frac) * 8000.0 / 4096.0 + float(self.coarse) * 8000.0) / 1000.0;
......@@ -21,6 +23,8 @@ class fd_timestamp(Structure):
class FineDelay:
BASE_ADDR = 0x84000
FREE_RUNNING = 0x10
WR_OFFLINE = 0x8
WR_READY = 0x1
......@@ -29,46 +33,63 @@ class FineDelay:
SYNC_LOCAL = 0x1
SYNC_WR = 0x2
def __init__(self, dev_path):
s = re.split("\/", dev_path)
self.fd = CDLL('../lib/libfinedelay.so')
if(s[0] == "local"):
print("Initializing local at %x" % int(s[1], 16))
self.handle = c_voidp(self.fd.fdelay_create_rawrabbit(int(s[1],16)));
elif(s[0] == "minibone"):
print("Initializing minibone at %s [%s]\n" %( s[1], s[2]))
self.handle = c_voidp(self.fd.fdelay_create_minibone(c_char_p(s[1]), c_char_p(s[2]), int(s[3], 16)));
if(self.fd.fdelay_init(self.handle) < 0):
def __init__(self, fd):
cwd = os.path.dirname(__file__)
self.fdelay = CDLL(cwd+'/../lib/libfinedelay.so')
self.handle = c_voidp(self.fdelay.fdelay_create_rawrabbit(c_int(fd), c_ulong(self.BASE_ADDR)));
if(c_int(self.fdelay.fdelay_load_firmware("spec_top.bin")) < 0):
print ("Firmware loader failed...");
sys.exit(-1)
print "Initialising Fine Delay board..."
if(self.fdelay.fdelay_init(self.handle) < 0):
print ("Init failed..");
# sys.exit(-1)
sys.exit(-1)
def conf_trigger(self, enable, termination):
self.fd.fdelay_configure_trigger(self.handle, c_int(enable), c_int(termination))
self.fdelay.fdelay_configure_trigger(self.handle, c_int(enable), c_int(termination))
def conf_output(self, channel, enable, delay, width):
self.fd.fdelay_configure_output(self.handle, c_int(channel), c_int(enable), c_ulonglong(delay), c_ulonglong(width))
self.fdelay.fdelay_configure_output(self.handle, c_int(channel), c_int(enable), c_ulonglong(delay), c_ulonglong(width), c_ulonglong(200000), c_int(1))
def conf_readout(self, enable):
self.fd.fdelay_configure_readout(self.handle, enable)
def conf_sync(self, mode):
self.fd.fdelay_configure_sync(self.handle, mode)
self.fdelay.fdelay_configure_readout(self.handle, enable)
# def conf_sync(self, mode):
# self.fdelay.fdelay_configure_sync(self.handle, mode)
def conf_pulsegen(self, channel, enable, t_start_utc, t_start_coarse, width, delta, count):
t = fd_timestamp(utc=c_ulonglong(t_start_utc), coarse=c_ulong(t_start_coarse))
#print "channel:%d enable:%d start_t:%d width:%d delta:%d count:%d"%(channel, enable, t.utc, width, delta, count)
self.fdelay.fdelay_configure_pulse_gen(self.handle, c_int(channel), c_int(enable), t,
c_ulonglong(width), c_ulonglong(delta), c_int(count))
def set_time(self, utc, coarse):
t = fd_timestamp(utc=c_ulonglong(utc), coarse=c_ulong(coarse))
self.fdelay.fdelay_set_time(self.handle, t)
def get_time(self):
t = fd_timestamp()
self.fdelay.fdelay_get_time(self.handle, byref(t))
return t
def get_sync_status(self):
htab = { self.FREE_RUNNING : "oscillator free-running",
self.WR_OFFLINE : "WR core offline",
self.WR_READY : "WR core ready",
self.WR_SYNCING : "Syncing local clock with WR",
self.WR_SYNCED : "Synced with WR" }
status = c_int(self.fd.fdelay_get_sync_status(self.handle));
# status = c_int(self.fdelay.fdelay_get_sync_status(self.handle));
# print("GetSyncStatus %x" % status.value);
return htab[status.value]
return "none"; #htab[status.value]
def read_ts(self):
buf = (fd_timestamp * 256)();
ptr = pointer(buf)
n = self.fd.fdelay_read(self.handle, ptr, 256)
n = self.fdelay.fdelay_read(self.handle, ptr, 256)
arr = [];
for i in range(0,n):
arr.append(buf[i])
......
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