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FMC DEL 1ns 4cha
Commit 9e5f27f9 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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fd_reset_generator: naming fixes after moving the code to a separate unit

parent d61f5071
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hdl/rtl/fd_reset_generator.vhd
View file @ 9e5f27f9
...@@ -28,13 +28,16 @@ architecture behavioral of fd_reset_generator is ...@@ -28,13 +28,16 @@ architecture behavioral of fd_reset_generator is
begin -- behavioral begin -- behavioral
regs_b <= c_fd_registers_init_value;
p_soft_reset : process(clk_sys_i) p_soft_reset : process(clk_sys_i)
begin begin
if rising_edge(clk_sys_i) then if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then if(rst_n_i = '0') then
rstn_host_sysclk <= '0'; rstn_host_sysclk <= '0';
else else
if(regs.rstr_wr_o = '1' and regs.rstr_o = c_RSTR_TRIGGER_VALUE) then if(regs_b.rstr_wr_o = '1' and regs_b.rstr_o = c_RSTR_TRIGGER_VALUE) then
rstn_host_sysclk <= '0'; rstn_host_sysclk <= '0';
else else
rstn_host_sysclk <= '1'; rstn_host_sysclk <= '1';
...@@ -43,6 +46,8 @@ begin -- behavioral ...@@ -43,6 +46,8 @@ begin -- behavioral
end if; end if;
end process; end process;
p_sync_reset_refclk : process(clk_ref_i) p_sync_reset_refclk : process(clk_ref_i)
begin begin
if rising_edge(clk_ref_i) then if rising_edge(clk_ref_i) then
......
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