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FMC DEL 1ns 4cha
Commit 41d6ec31 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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testbench: wip

parent 11309c73
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Showing with 245 additions and 255 deletions
hdl/include/regs/fd_main_regs.vh
View file @ 41d6ec31
......@@ -12,7 +12,7 @@
`define FD_GCR_INPUT_EN_OFFSET 1
`define FD_GCR_INPUT_EN 32'h00000002
`define FD_GCR_DDR_LOCKED_OFFSET 2
`define FD_GCR_DDR_LOCKED 32'h0000CAL0004
`define FD_GCR_DDR_LOCKED 32'h00000004
`define FD_GCR_FMC_PRESENT_OFFSET 3
`define FD_GCR_FMC_PRESENT 32'h00000008
`define ADDR_FD_TCR 8'hc
......@@ -55,12 +55,6 @@
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define FD_TDCSR_IDELAY_RST_OFFSET 9
`define FD_TDCSR_IDELAY_RST 32'h00000200
`define FD_TDCSR_IDELAY_CAL_OFFSET 10
`define FD_TDCSR_IDELAY_CAL 32'h00000400
`define FD_TDCSR_IDELAY_INC_OFFSET 11
`define FD_TDCSR_IDELAY_INC 32'h00000800
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......@@ -163,28 +157,34 @@
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define ADDR_FD_FMC_SLOT_ID 8'h7c
`define FD_FMC_SLOT_ID_SLOT_ID_OFFSET 0
`define FD_FMC_SLOT_ID_SLOT_ID 32'h0000000f
`define ADDR_FD_IODELAY_ADJ 8'h80
`define FD_IODELAY_ADJ_N_TAPS_OFFSET 0
`define FD_IODELAY_ADJ_N_TAPS 32'h0000003f
`define ADDR_FD_EIC_IDR 8'ha0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IDR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IDR_DMTD_SPLL 32'h00000002
`define FD_EIC_IDR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IDR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IER 8'h84
`define ADDR_FD_EIC_IER 8'ha4
`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IER_DMTD_SPLL_OFFSET 1
`define FD_EIC_IER_DMTD_SPLL 32'h00000002
`define FD_EIC_IER_SYNC_STATUS_OFFSET 2
`define FD_EIC_IER_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IMR 8'h88
`define ADDR_FD_EIC_IMR 8'ha8
`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IMR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IMR_DMTD_SPLL 32'h00000002
`define FD_EIC_IMR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IMR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_ISR 8'h8c
`define ADDR_FD_EIC_ISR 8'hac
`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_ISR_DMTD_SPLL_OFFSET 1
......
hdl/include/vme64x_bfm/svec_vme_buffers.svh
View file @ 41d6ec31
......@@ -162,6 +162,16 @@ function automatic bit[5:0] _gen_ga(int slot);
return {^slot_id, ~slot_id};
endfunction // _gen_ga
function automatic bit[4:0] _gen_ga_convention(int slot);
bit[4:0] slot_id = slot;
return {~slot_id};
endfunction // _gen_ga
function automatic bit _gen_gap_convention(int slot);
bit[4:0] slot_id = slot;
return ^slot_id;
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
......@@ -190,4 +200,30 @@ endfunction // _gen_ga
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
\ No newline at end of file
`define WIRE_VME_PINS_CONVENTION(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_SYSRESET_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga_convention(slot_id)),\
.VME_GAP_i(_gen_gap_convention(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_IRQ_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
hdl/testbench/svec_wr_top/Manifest.py
View file @ 41d6ec31
ctrls = ["bank3_32b_32b"]
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
sim_tool="modelsim"
sim_top="main"
include_dirs = ["../../include/vme64x_bfm",
"../../include/wb", "../../include",
"../../ip_cores/general-cores/modules/wishbone/wb_spi/",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
syn_device = "xc6slx45t"
sim_tool = "modelsim"
sim_top = "main"
top_module = "main"
files = ["main.sv","buildinfo_pkg.vhd"]
include_dirs = ["../../include/wb", "../../include/vme64x_bfm", "../../include" ];
syn_device="xc6slx150t"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/svec" ] }
modules = {"local": ["../../top/svec" ]}
#try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
#except:
# pass
hdl/testbench/svec_wr_top/fdelay_board.svh
View file @ 41d6ec31
......@@ -223,34 +223,34 @@ module fdelay_board (
endmodule // main
`define WIRE_FINE_DELAY_PINS(fmc_index,iface) \
.fd``fmc_index``_tdc_start_p_i (iface.core.tdc_start_p), \
.fd``fmc_index``_tdc_start_n_i (iface.core.tdc_start_n), \
.fd``fmc_index``_clk_ref_p_i (iface.core.clk_ref_p), \
.fd``fmc_index``_clk_ref_n_i (iface.core.clk_ref_n), \
.fd``fmc_index``_trig_a_i (iface.core.trig_a), \
.fd``fmc_index``_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fd``fmc_index``_tdc_d_b (iface.core.tdc_d), \
.fd``fmc_index``_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fd``fmc_index``_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fd``fmc_index``_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fd``fmc_index``_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fd``fmc_index``_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fd``fmc_index``_led_trig_o (iface.core.led_trig), \
.fd``fmc_index``_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fd``fmc_index``_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fd``fmc_index``_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fd``fmc_index``_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fd``fmc_index``_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fd``fmc_index``_spi_sclk_o (iface.core.spi_sclk), \
.fd``fmc_index``_spi_mosi_o (iface.core.spi_mosi), \
.fd``fmc_index``_spi_miso_i (iface.core.spi_miso), \
.fd``fmc_index``_delay_len_o (iface.core.delay_len), \
.fd``fmc_index``_delay_val_o (iface.core.delay_val), \
.fd``fmc_index``_delay_pulse_o (iface.core.delay_pulse), \
.fd``fmc_index``_dmtd_clk_o (iface.core.dmtd_clk), \
.fd``fmc_index``_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fd``fmc_index``_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fd``fmc_index``_pll_status_i (iface.core.pll_status), \
.fd``fmc_index``_ext_rst_n_o (iface.core.ext_rst_n), \
.fd``fmc_index``_onewire_b (iface.core.onewire)
.fmc``fmc_index``_fd_tdc_start_p_i (iface.core.tdc_start_p), \
.fmc``fmc_index``_fd_tdc_start_n_i (iface.core.tdc_start_n), \
.fmc``fmc_index``_fd_clk_ref_p_i (iface.core.clk_ref_p), \
.fmc``fmc_index``_fd_clk_ref_n_i (iface.core.clk_ref_n), \
.fmc``fmc_index``_fd_trig_a_i (iface.core.trig_a), \
.fmc``fmc_index``_fd_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fmc``fmc_index``_fd_tdc_d_b (iface.core.tdc_d), \
.fmc``fmc_index``_fd_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fmc``fmc_index``_fd_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fmc``fmc_index``_fd_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fmc``fmc_index``_fd_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fmc``fmc_index``_fd_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fmc``fmc_index``_fd_led_trig_o (iface.core.led_trig), \
.fmc``fmc_index``_fd_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fmc``fmc_index``_fd_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fmc``fmc_index``_fd_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fmc``fmc_index``_fd_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fmc``fmc_index``_fd_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fmc``fmc_index``_fd_spi_sclk_o (iface.core.spi_sclk), \
.fmc``fmc_index``_fd_spi_mosi_o (iface.core.spi_mosi), \
.fmc``fmc_index``_fd_spi_miso_i (iface.core.spi_miso), \
.fmc``fmc_index``_fd_delay_len_o (iface.core.delay_len), \
.fmc``fmc_index``_fd_delay_val_o (iface.core.delay_val), \
.fmc``fmc_index``_fd_delay_pulse_o (iface.core.delay_pulse), \
.fmc``fmc_index``_fd_dmtd_clk_o (iface.core.dmtd_clk), \
.fmc``fmc_index``_fd_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fmc``fmc_index``_fd_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fmc``fmc_index``_fd_pll_status_i (iface.core.pll_status), \
.fmc``fmc_index``_fd_ext_rst_n_o (iface.core.ext_rst_n), \
.fmc``fmc_index``_fd_onewire_b (iface.core.onewire)
hdl/testbench/svec_wr_top/main.sv
View file @ 41d6ec31
......@@ -105,7 +105,6 @@ module main;
`DECLARE_VME_BUFFERS(VME.slave);
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
......@@ -116,7 +115,7 @@ module main;
.rst_n_i(rst_n),
`WIRE_VME_PINS(8),
`WIRE_VME_PINS_CONVENTION(8),
`WIRE_FINE_DELAY_PINS(0, I_fmc0),
`WIRE_FINE_DELAY_PINS(1, I_fmc1)
);
......@@ -169,6 +168,7 @@ module main;
Timestamp dly, t_start;
CSimDrv_FineDelay drv0;
CSimDrv_FineDelay drv1;
uint64_t d;
#20us;
......@@ -181,17 +181,19 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv1 = new(acc, 'h80020000);
drv1.init();
drv0.set_idelay_taps(30);
drv0.set_idelay_taps(5);
t_start=new;
/* t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
drv0.config_output(1, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001100, -1);
drv0.config_output(2, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001200, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1); */
$display("Init done");
......
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ 41d6ec31
......@@ -42,26 +42,10 @@ class CSimDrv_FineDelay;
task set_idelay_taps( int taps );
uint64_t tdcsr;
readl(`ADDR_FD_TDCSR, tdcsr);
// calibrate the iodelay
writel( `ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CAL );
#3us;
writel( `ADDR_FD_TDCSR , tdcsr );
$display("Set IDELAY tap count = %d", taps);
$display("Set Idelay taps : %d\n", taps);
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_RST );
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_INC );
for(int i = 0; i<taps;i++)
begin
writel(`ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CE | `FD_TDCSR_IDELAY_INC );
#1us;
end
writel(`ADDR_FD_IODELAY_ADJ, taps);
endtask // set_idelay_taps
......
hdl/testbench/svec_wr_top/wave.do
View file @ 41d6ec31
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group VME /main/rst_n
add wave -noupdate -group VME /main/clk_125m
add wave -noupdate -group VME /main/clk_20m
add wave -noupdate -group VME /main/VME_AS_n
add wave -noupdate -group VME /main/VME_RST_n
add wave -noupdate -group VME /main/VME_WRITE_n
add wave -noupdate -group VME /main/VME_AM
add wave -noupdate -group VME /main/VME_DS_n
add wave -noupdate -group VME /main/VME_BERR
add wave -noupdate -group VME /main/VME_DTACK_n
add wave -noupdate -group VME /main/VME_RETRY_n
add wave -noupdate -group VME /main/VME_RETRY_OE
add wave -noupdate -group VME /main/VME_LWORD_n
add wave -noupdate -group VME /main/VME_ADDR
add wave -noupdate -group VME /main/VME_DATA
add wave -noupdate -group VME /main/VME_BBSY_n
add wave -noupdate -group VME /main/VME_IRQ_n
add wave -noupdate -group VME /main/VME_IACKIN_n
add wave -noupdate -group VME /main/VME_IACK_n
add wave -noupdate -group VME /main/VME_IACKOUT_n
add wave -noupdate -group VME /main/VME_DTACK_OE
add wave -noupdate -group VME /main/VME_DATA_DIR
add wave -noupdate -group VME /main/VME_DATA_OE_N
add wave -noupdate -group VME /main/VME_ADDR_DIR
add wave -noupdate -group VME /main/VME_ADDR_OE_N
add wave -noupdate -group VME /main/trig0
add wave -noupdate -group VME /main/trig1
add wave -noupdate -group VME /main/out0
add wave -noupdate -group VME /main/out1
add wave -noupdate -group VME /main/pulse_enable
add wave -noupdate -group VME /main/out0_delayed
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/BUSY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DOUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/TOUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CAL
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CE
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CLK
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDATAIN
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/INC
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK0
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODATAIN
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/RST
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/T
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/COUNTER_WRAPAROUND_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATA_RATE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DELAY_SRC_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY2_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_MODE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_TYPE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODELAY_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/SERDES_MODE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/SIM_TAPDELAY_VALUE_BINARY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/Tstep
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/COUNTER_WRAPAROUND_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DELAY_SRC_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_MODE_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDELAY_TYPE_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/SERDES_MODE_PAD
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/GSR_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/rst_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ce_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/inc_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/cal_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_out_sig
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_out
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_out
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_out_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/tout_out_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_pe_one_shot
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_ne_one_shot
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_pe_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_pe_dly1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_ne_dly
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/busy_out_ne_dly1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sdo_out_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ioclk0_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ioclk1_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ioclk_int
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/first_edge
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sat_at_max_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/rst_to_half_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ignore_rst
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/force_rx_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/force_dly_dir_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/output_delay_off
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/input_delay_off
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/isslave
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/encasc
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/counter_wraparound_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/data_rate_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/serdes_mode_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/odelay_value_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_value_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sim_tap_delay_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_type_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_mode_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_src_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay2_value_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/attr_err_flag
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/cal_count
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/cal_delay
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/max_delay
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/half_max
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_pe_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_ne_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_pe_clk
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_ne_clk
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/first_time_pe
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/first_time_ne
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_m_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_s_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_m_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_pe_s_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_m_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_s_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_m_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/idelay_val_ne_s_reg1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_reached
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_reached_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_reached_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_working
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_working_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_working_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_ignore
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_pe_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay_val_ne_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/odelay_val_pe_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/odelay_val_ne_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_reached
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_reached_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_reached_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_working
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_working_1
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_working_2
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_ignore
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay1_in
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/delay2_in
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/calibrate
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/calibrate_done
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/sync_to_data_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/pci_ce_reg
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/BUSY_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT2_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DOUT_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/TOUT_OUT
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/BUSY_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT2_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DATAOUT_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/DOUT_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/TOUT_OUTDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CAL_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CE_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CLK_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDATAIN_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/INC_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK0_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK1_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODATAIN_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/RST_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/T_ipd
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CAL_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CE_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/CLK_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IDATAIN_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/INC_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK0_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/IOCLK1_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/ODATAIN_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/RST_INDELAY
add wave -noupdate -expand -group Delay0 /main/DUT/cmp_fd_tdc_start_delay0/T_INDELAY
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_ref_0_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_ref_180_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_sys_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/clk_dmtd_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rst_n_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dcm_reset_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dcm_locked_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/trig_a_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_cal_pulse_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_start_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_fb_in_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_fb_out_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_samp_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/led_trig_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/ext_rst_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/pll_status_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_d_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_d_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_d_oen_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_emptyf_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_alutrigger_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_wr_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_rd_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_start_dis_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/acam_stop_dis_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_dac_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_pll_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_gpio_n_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_sclk_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_mosi_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_miso_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/delay_len_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/delay_val_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/delay_pulse_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_link_up_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_time_valid_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_cycles_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_utc_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_clk_aux_lock_en_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_clk_aux_locked_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_clk_dmtd_locked_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_dac_value_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_dac_wr_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_en_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_scl_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_scl_oen_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_scl_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_sda_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_sda_oen_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/i2c_sda_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/fmc_present_n_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_inc_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_cal_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_ce_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/idelay_rst_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_adr_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_dat_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_dat_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_sel_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_cyc_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_stb_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_we_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_ack_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_stall_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/wb_irq_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_seconds_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_cycles_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_frac_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_valid_o
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_seconds_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_cycles_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_frac_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/outx_valid_i
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_o
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add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_utc
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add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_valid
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_ts
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_valid
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_valid_masked
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_in_ts
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_source
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_valid
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add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rbuf_mux_q
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/master_csync_p1
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/master_csync_utc
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/master_csync_coarse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rst_n_sys
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/rst_n_ref
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tsbcr_read_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/fid_read_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/irq_rbuf
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/irq_spll
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/irq_sync
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add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/chx_delay_idle
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cnx_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cnx_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/slave_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/slave_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_fromwb
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_csync
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_spi
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_tsu
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_rbuf
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_local
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb_dmtd
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/regs_towb
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_en_int
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/owr_int
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_acam
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/gen_cal_pulse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cal_pulse_mask
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/cal_pulse_trigger
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tm_dac_val_int
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tcr_rd_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tag_valid_masked
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_pattern
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/csync_pps
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/tdc_cal_pulse
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtr_in_rd_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtr_out_rd_ack
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/pwm_count
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/pwm_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_dac_n
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_pll_n
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_cs_gpio_n
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/spi_mosi
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dmtd_tag_stb
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_tag_in
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/dbg_tag_out
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_ntaps
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_cnt
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_div
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_tick
add wave -noupdate -expand -group fd0 /main/DUT/U_FineDelay_Core0/iodelay_cal_done
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9101898590 fs} 0}
configure wave -namecolwidth 183
WaveRestoreCursors {{Cursor 1} {23947022 ps} 0}
configure wave -namecolwidth 486
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -195,4 +156,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {226247193600 fs}
WaveRestoreZoom {23573029 ps} {24321015 ps}
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