description = "Writing 0xDEADBEEF into this register will trigger a full reset of the \ fine delay core";
type = PASS_THROUGH;
size = 32;
};
};
name = "Fine Delay Wishbone slave";
hdl_entity = "fd_wishbone_slave";
prefix = "fd";
reg {
name = "Reset Register";
prefix = "RSTR";
field {
name = "Reset trigger";
description = "Writing 0xDEADBEEF into this register will trigger a full reset of the \ fine delay core";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "ID Register";
...
...
@@ -33,32 +34,32 @@ peripheral {
};
reg {
name = "Global Control Register";
prefix = "GCR";
field {
clock = "clk_ref_i";
reg {
name = "Global Control Register";
prefix = "GCR";
field {
clock = "clk_ref_i";
name = "Bypass delay block";
prefix = "BYPASS";
description = "0: normal operation (fine-delay)\
name = "Bypass delay block";
prefix = "BYPASS";
description = "0: normal operation (fine-delay)\
1: TDC and delay lines controlled from the host";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "Enable trigger input";
prefix = "INPUT_EN";
description = "";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
clock = "clk_ref_i";
name = "Enable trigger input";
prefix = "INPUT_EN";
description = "";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Internal Counter Sync";
...
...
@@ -85,123 +86,154 @@ peripheral {
prefix = "WR_READY";
type = BIT;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TDC Address/Data Register";
prefix = "TAR";
field {
clock = "clk_ref_i";
name = "DATA";
prefix = "DATA";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
clock = "clk_ref_i";
name = "ADDR";
prefix = "ADDR";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TDC control/status reg";
prefix = "TDCSR";
field {
name = "Start TDC write";
prefix = "WRITE";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Start TDC read";
prefix = "READ";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Error flag";
prefix = "ERR";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Interrupt flag";
prefix = "INT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Load flag";
prefix = "LOAD";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Empty flag";
prefix = "EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Start disable";
prefix = "START_DIS";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Start enable";
prefix = "START_EN";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Start disable";
prefix = "STOP_DIS";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Start enable";
prefix = "STOP_EN";
type = MONOSTABLE;
};
};
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TDC Address/Data Register";
prefix = "TAR";
field {
clock = "clk_ref_i";
name = "DATA";
prefix = "DATA";
type = SLV;
size = 28;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
clock = "clk_ref_i";
name = "ADDR";
prefix = "ADDR";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TDC control/status reg";
prefix = "TDCSR";
field {
name = "Start TDC write";
prefix = "WRITE";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Start TDC read";
prefix = "READ";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Error flag";
prefix = "ERR";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Interrupt flag";
prefix = "INT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Load flag";
prefix = "LOAD";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Empty flag";
prefix = "EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
clock = "clk_ref_i";
name = "Start enable";
prefix = "STOP_EN";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Start disable";
prefix = "START_DIS";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Stop enable";
prefix = "START_EN";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Stop disable";
prefix = "STOP_DIS";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "write 1: Pulse the Alutrigger line";
prefix = "ALUTRIG";
type = MONOSTABLE;
};
};
reg {
prefix = "CALR";
name = "Calibration register";
field {
clock = "clk_ref_i";
name = "Triggers calibration pulses";
description = "write 1: Generates synchronous calibration pulses the channels selected in PSEL field.";
prefix = "CAL_PULSE";
type = MONOSTABLE;
};
field {
clock = "clk_ref_i";
name = "Enable pulse generation";
description = "1: enable generation of calibration pulses on the output corresponding to the written bit\
0: disable generation of these pulses";
prefix = "PSEL";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
...
...
@@ -216,85 +248,85 @@ peripheral {
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
prefix = "ATMCR";
name = "Acam Timestamp Merging Control Register";
description = "Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM";
field {
name = "Wraparound Coarse Threshold";
prefix = "C_THR";
size = 4;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Wraparound Fine Threshold";
prefix = "F_THR";
size = 23;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
prefix = "ASOR";
name = "Acam Start Offset Register";
description = "";
field {
name = "Start Offset";
prefix = "OFFSET";
size = 23;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Raw Input Events Counter Register ";
prefix = "IECRAW";
field {
name = "Number of raw events";
description = "Number of all input pulses detected by the timestamper";
type = SLV;
size = 32;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev= WRITE_ONLY;
};
};
reg {
name = "Tagged Input Events Counter Register ";
prefix = "IECTAG";
field {
name = "Number of tagged events";
description = "Number of all input pulses which passed the width checks and have produced valid timestamps.";
type = SLV;
size = 32;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev= WRITE_ONLY;
};
};
reg {
name = "Input Event Processing Delay Register";
prefix = "IEPD";
};
};
reg {
prefix = "ATMCR";
name = "Acam Timestamp Merging Control Register";
description = "Register controlling the merging of the fine timestamps prouced by Acam with the coarse timestamps gatheret by the FPGA. These values are hardware-specific. The register should be loaded with the paramete 'ATMCR' from the mezzanine's configuration EEPROM";
field {
name = "Wraparound Coarse Threshold";
prefix = "C_THR";
size = 4;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Wraparound Fine Threshold";
prefix = "F_THR";
size = 23;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
prefix = "ASOR";
name = "Acam Start Offset Register";
description = "";
field {
name = "Start Offset";
prefix = "OFFSET";
size = 23;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Raw Input Events Counter Register ";
prefix = "IECRAW";
field {
name = "Number of raw events";
description = "Number of all input pulses detected by the timestamper";
type = SLV;
size = 32;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev= WRITE_ONLY;
};
};
reg {
name = "Tagged Input Events Counter Register ";
prefix = "IECTAG";
field {
name = "Number of tagged events";
description = "Number of all input pulses which passed the width checks and have produced valid timestamps.";
type = SLV;
size = 32;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev= WRITE_ONLY;
};
};
reg {
name = "Input Event Processing Delay Register";
prefix = "IEPD";
field {
name = "Reset stats";
...
...
@@ -302,20 +334,20 @@ peripheral {
description = "Write 1: resets the delay/pulse count counters (IECRAW, IECTAG and IEPD_WDELAY)\
write 0: no effect";
type = MONOSTABLE;
clock = "clk_ref_i";
clock = "clk_ref_i";
};
field {
name = "Processing delay";
description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
field {
name = "Processing delay";
description = "Worst-case delay between the input event and the generation of its timestamp. Expressed as a number of 125 MHz clock cycles.";
prefix = "PDELAY";
type = SLV;
size = 8;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
type = SLV;
size = 8;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- reg {
-- name = "SPI Control Register";
...
...
@@ -332,7 +364,7 @@ peripheral {
-- access_dev = READ_WRITE;
-- access_bus = READ_WRITE;
-- };
-- field {
-- name = "Select DAC";
-- prefix = "SEL_DAC";
...
...
@@ -405,7 +437,7 @@ peripheral {
};
reg {
reg {
name = "Reference Clock Frequency Register";
prefix = "RCFR";
description = "Current frequency of the reference clock. Used for testing/calibration purposes.";
...
...
@@ -420,55 +452,55 @@ peripheral {
}
};
reg {
name = "Timestamp Buffer Control Register";
prefix = "TSBCR";
field {
name = "Buffer enable";
prefix = "ENABLE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Buffer purge";
prefix = "PURGE";
type = MONOSTABLE;
};
field {
name = "Reset TS Sequence Number";
prefix = "RST_SEQ";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Buffer full";
prefix = "FULL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Buffer empty";
prefix = "EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
reg {
name = "Timestamp Buffer Control Register";
prefix = "TSBCR";
field {
name = "Buffer enable";
prefix = "ENABLE";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Buffer purge";
prefix = "PURGE";
type = MONOSTABLE;
};
field {
name = "Reset TS Sequence Number";
prefix = "RST_SEQ";
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Buffer full";
prefix = "FULL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Buffer empty";
prefix = "EMPTY";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
irq {
name = "TS Buffer not empty";
trigger = LEVEL_0;
prefix = "ts_buf_notempty";
};
irq {
name = "TS Buffer not empty";
trigger = LEVEL_0;
prefix = "ts_buf_notempty";
};
reg {
name = "Timestamp Buffer Readout UTC Register";
...
...
@@ -479,7 +511,7 @@ peripheral {
size = 32;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
...
...
@@ -492,60 +524,60 @@ peripheral {
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Timestamp Buffer Readout Fine / Seq ID Register";
prefix = "TSBR_FID";
field {
name = "Fine Value [in phase units]";
prefix = "FINE";
size = 12;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Sequence ID";
prefix = "SEQID";
align = 16;
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "advance_rbuf_o";
};
};
fifo_reg {
direction = CORE_TO_BUS;
size = 256;
prefix = "RAWFIFO";
name = "RAW FIFO";
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL};
clock = "clk_ref_i";
field {
name = "RawFrac";
prefix = "FRAC";
size = 28;
type = SLV;
};
field {
name = "RawCoarse";
prefix = "COARSE";
size = 28;
type = SLV;
};
};
reg {
name = "Timestamp Buffer Readout Fine / Seq ID Register";
prefix = "TSBR_FID";
field {
name = "Fine Value [in phase units]";
prefix = "FINE";
size = 12;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Sequence ID";
prefix = "SEQID";
align = 16;
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "advance_rbuf_o";
};
};
fifo_reg {
direction = CORE_TO_BUS;
size = 256;
prefix = "RAWFIFO";
name = "RAW FIFO";
flags_bus = {FIFO_EMPTY};
flags_dev = {FIFO_FULL};
clock = "clk_ref_i";
field {
name = "RawFrac";
prefix = "FRAC";
size = 28;
type = SLV;
};
field {
name = "RawCoarse";
prefix = "COARSE";
size = 28;
type = SLV;
};
};
};
channel_template = {
...
...
@@ -587,176 +619,176 @@ channel_template = {
Note that the time written to [U/C/F]START must be bigger by at least 200 ns than the value of the UTC counter at the moment of arming the pulse generator. In practice, the safety margin should be much bigger, as it's affected by the non-determinism of the operating system.";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "clk_ref_i";
};
field {
name = "Pulse generator triggered";
prefix = "PG_TRIG";
description = "read 1: pulse generator has been triggered and produced a pulse\
read 0: pulse generator is busy or hasn't triggered yet";
type = BIT;
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Start Delay Update";
prefix = "UPDATE";
description = "write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers\
clock = "clk_ref_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Start Delay Update";
prefix = "UPDATE";
description = "write 1: Starts delay update procedure. The start and end times from [U/C/F][START/END] will be transferred in an atomic way to the internal delay/pulse generator registers\
write 0: no effect.";
type = MONOSTABLE;
clock = "clk_ref_i";
};
field {
name = "Delay Update Done";
prefix = "UPD_DONE";
description = "read 1: The delays from [U/C/F][START/END] have been loaded into internal registers\
type = MONOSTABLE;
clock = "clk_ref_i";
};
field {
name = "Delay Update Done";
prefix = "UPD_DONE";
description = "read 1: The delays from [U/C/F][START/END] have been loaded into internal registers\
read 0: update operation in progress";
clock = "clk_ref_i";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Force Calibration Pulse";
prefix = "FORCE_CP";
description = "write 1: preloads the delay line with the contents of FRR register and produces a single-cycle (8ns) pulse at the beginning of the ACAM Start period. Used for self-calibration purposes\
clock = "clk_ref_i";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Force Calibration Delay";
prefix = "FORCE_DLY";
description = "write 1: preloads the delay line with the contents of FRR register. Used for self-calibration purposes.\
write 0: no effect";
clock = "clk_ref_i";
type = MONOSTABLE;
};
clock = "clk_ref_i";
type = MONOSTABLE;
};
field {
name = "Output Polarity";
prefix = "POL";
description = "1: output is active HIGH\
field {
name = "Output Polarity";
prefix = "POL";
description = "1: output is active HIGH\
0: output is active LOW";
clock = "clk_ref_i";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Fine Range Register (channel %d)";
prefix = "FRR%d";
description = "Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.";
field {
name = "Fine Range";
size = 10;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse start time / offset (UTC part, channel %d)";
prefix = "U_START%d";
description = "UTC part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
name = "UTC seconds";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse start time / offset (8 ns cycles, channel %d)";
prefix = "C_START%d";
description = "Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
name = "Refclk cycles";
size = 28;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse start time / offset (sub-cycle fine part, channel %d)";
prefix = "F_START%d";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
name = "Fractional part";
size = 12;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
clock = "clk_ref_i";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Fine Range Register (channel %d)";
prefix = "FRR%d";
description = "Delay line tap setting at which the line generates an 8 ns (one cycle) longer delay than when set to 0.";
field {
name = "Fine Range";
size = 10;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse start time / offset (UTC part, channel %d)";
prefix = "U_START%d";
description = "UTC part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
name = "UTC seconds";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse start time / offset (8 ns cycles, channel %d)";
prefix = "C_START%d";
description = "Sub-second part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
name = "Refclk cycles";
size = 28;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse start time / offset (sub-cycle fine part, channel %d)";
prefix = "F_START%d";
description = "Sub-clock cycle part of the pulse start absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
name = "Fractional part";
size = 12;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse end time / offset (UTC part, channel %d)";
prefix = "U_END%d";
description = "UTC part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
name = "UTC seconds";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse end time / offset (8 ns cycles, channel %d)";
prefix = "C_END%d";
description = "Sub-second part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
name = "Refclk cycles";
size = 28;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse end time / offset (sub-cycle fine part, channel %d)";
prefix = "F_END%d";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
name = "Fractional part";
size = 12;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse end time / offset (UTC part, channel %d)";
prefix = "U_END%d";
description = "UTC part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode).";
field {
name = "UTC seconds";
size = 32;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse end time / offset (8 ns cycles, channel %d)";
prefix = "C_END%d";
description = "Sub-second part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Expressed as a number of 125 MHz clock cycles. Acceptable range: 0 to 124999999.";
field {
name = "Refclk cycles";
size = 28;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Pulse end time / offset (sub-cycle fine part, channel %d)";
prefix = "F_END%d";
description = "Sub-clock cycle part of the pulse end absolute time (when in PG mode) / offset from trigger (when in delay mode). Scales linearly to <0..8 ns>: 0 = 0 ps, 4095 = 7999 ps.";
field {
name = "Fractional part";
size = 12;
type = SLV;
clock = "clk_ref_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
...
...
@@ -769,10 +801,10 @@ function generate_channels(n)
