| ... | ... | @@ -94,39 +94,39 @@ use](https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/uploads/9a7b66f98f15 |
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</tr>
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<tr class="even">
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|
<td>01-04-2013</td>
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|
<td>Specification written</td>
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<td>Specification written.</td>
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</tr>
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<tr class="odd">
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|
<td>24-04-2013</td>
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|
<td>Boards received and powered on, no smoke so far. One bug fixed (no 3.3V routed to the VCXO and PLL)</td>
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|
<td>Boards received and powered on, no smoke so far. One bug fixed (no 3.3V routed to the VCXO and PLL).</td>
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</tr>
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<tr class="even">
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|
<td>08-05-2013</td>
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|
<td><a href="https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo">Proof-of-concept</a> VHDL and software</td>
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|
<td><a href="https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo">Proof-of-concept</a> VHDL and software.</td>
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</tr>
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|
<tr class="odd">
|
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|
<td>20-11-2013</td>
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|
<td>Specification of new version (v2) of the board including functionality of pulse generation with <50 ps RMS jitter and programmable fine delay</td>
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|
<td>Specification of new version (v2) of the board including functionality of pulse generation with <50 ps RMS jitter and programmable fine delay.</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
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|
|
<td>22-11-2013</td>
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|
<td>LNLS put order for the v2 design</td>
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|
<td>LNLS put order for the v2 design.</td>
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|
</tr>
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|
<tr class="odd">
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|
<td>29-12-2013</td>
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|
<td>Schematics of v2 at repository - ready for review</td>
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|
<td>Schematics of v2 at repository - ready for review.</td>
|
|
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|
</tr>
|
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|
<tr class="even">
|
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|
|
<td>20-01-2014</td>
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|
|
<td>Reviewed schematics of v2: [Review-jan-2014](Review-jan-2014)</td>
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|
<td>Reviewed schematics of v2: [Review-jan-2014](Review-jan-2014).</td>
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</tr>
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|
<tr class="odd">
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|
<td>24-09-2014</td>
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|
<td>V2 Design released in [EDMS](https://edms.cern.ch/nav/EDA-03010-V1-0)</td>
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|
<td>V2 Design released in [EDMS](https://edms.cern.ch/nav/EDA-03010-V1-0).</td>
|
|
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</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>15-01-2015</td>
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|
|
<td>4 cards built and powered</td>
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|
|
<td>4 EDA-03010-V1-0 cards built and powered ([order](https://edh.cern.ch/Document/SupplyChain/DAI/5814761)).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>24-08-2015</td>
|
| ... | ... | @@ -138,14 +138,22 @@ use](https://www.ohwr.org/project/fmc-dac-600m-12b-1cha-dds/uploads/9a7b66f98f15 |
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|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>30-09-2015</td>
|
|
|
|
<td>Measured jitter 15 ps RMS. Goal is <2 ns. Should replace PLL + VCXO (500 MHz) by an AD9516, add test support logic (LDO type)</td>
|
|
|
|
<td>Measured jitter 15 ps RMS. Goal is <2 ns. Should replace PLL + VCXO (500 MHz) by an AD9516, add test support logic (LDO type).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>04-04-2016</td>
|
|
|
|
<td>5 EDA-03010-V1-0 cards with <a href="https://edms.cern.ch/document/1577910/1">modifications</a> built and received ([order](https://edh.cern.ch/Document/SupplyChain/DAI/6279829)).</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>09-07-2018</td>
|
|
|
|
<td>Opening up project to investigate RF timing distribution over WR.</td>
|
|
|
|
</tr>
|
|
|
|
</tbody>
|
|
|
|
</table>
|
|
|
|
|
|
|
|
-----
|
|
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|
|
|
|
|
6 January 2016
|
|
|
|
9 July 2018
|
|
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|
| ... | ... | |
