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Measured jitter 15 ps RMS. Goal is <2 ns. Should replace PLL + VCXO(500 MHz)... authored by Erik van der Bij's avatar Erik van der Bij 
Measured jitter 15 ps RMS. Goal is <2 ns. Should replace PLL + VCXO(500 MHz) by an AD9516, add test support logic (LDO type)
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<td>29-09-2015</td>
<td>PTS not yet tested. Some components need to be changed, V1-1 needs to be made. Spurs on phase noise need investigation.</td>
<td>PTS not yet tested. Some components need to be changed. Spurs on phase noise need investigation.</td>
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<td>30-09-2015</td>
<td>Measured jitter 15 ps RMS. Goal is &lt;2 ns. Should replace PLL + VCXO (500 MHz) by an AD9516, add test support logic (LDO type)</td>
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