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......@@ -104,90 +104,28 @@ Rabbit](https://www.ohwr.org/project/white-rabbit/wiki) network.
## Status
<table>
<tbody>
<tr class="odd">
<td><strong>Date</strong></td>
<td><b> Event </b></td>
</tr>
<tr class="even">
<td>01-04-2013</td>
<td>Specification written.</td>
</tr>
<tr class="odd">
<td>24-04-2013</td>
<td>Boards received and powered on, no smoke so far. One bug fixed (no 3.3V routed to the VCXO and PLL).</td>
</tr>
<tr class="even">
<td>08-05-2013</td>
<td><a href="https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo">Proof-of-concept</a> VHDL and software.</td>
</tr>
<tr class="odd">
<td>20-11-2013</td>
<td>Specification of new version (v2) of the board including functionality of pulse generation with &lt;50 ps RMS jitter and programmable fine delay.</td>
</tr>
<tr class="even">
<td>22-11-2013</td>
<td>LNLS put order for the v2 design.</td>
</tr>
<tr class="odd">
<td>29-12-2013</td>
<td>Schematics of v2 at repository - ready for review.</td>
</tr>
<tr class="even">
<td>20-01-2014</td>
<td>Reviewed schematics of v2: [Review-jan-2014](Review-jan-2014).</td>
</tr>
<tr class="odd">
<td>24-09-2014</td>
<td>V2 Design released in [EDMS](https://edms.cern.ch/nav/EDA-03010-V1-0).</td>
</tr>
<tr class="even">
<td>15-01-2015</td>
<td>4 EDA-03010-V1-0 cards built and powered ([order](https://edh.cern.ch/Document/SupplyChain/DAI/5814761)).</td>
</tr>
<tr class="odd">
<td>24-08-2015</td>
<td>Production test system written. Not yet tested.</td>
</tr>
<tr class="even">
<td>29-09-2015</td>
<td>PTS not yet tested. Some components need to be changed. Spurs on phase noise need investigation.</td>
</tr>
<tr class="odd">
<td>30-09-2015</td>
<td>Measured jitter 15 ps RMS. Goal is &lt;2 ns. Should replace PLL + VCXO (500 MHz) by an AD9516, add test support logic (LDO type).</td>
</tr>
<tr class="even">
<td>04-04-2016</td>
<td>5 EDA-03010-V1-0 cards with <a href="https://edms.cern.ch/document/1577910/1">modifications</a> built and received ([order](https://edh.cern.ch/Document/SupplyChain/DAI/6279829)).</td>
</tr>
<tr class="odd">
<td>09-07-2018</td>
<td>Opening up project to investigate RF timing distribution over WR.</td>
</tr>
<tr class="even">
<td>08-11-2018</td>
<td>Proposal to create a v3.0 to address some v2.0 issues.</td>
</tr>
<tr class="odd">
<td>28-11-2018</td>
<td>Received v3.0 schematics from Creotech [Review-dec-2018](Review-dec-2018).</td>
</tr>
<tr class="even">
<td>14-12-2018</td>
<td>Schematic review v3.0 [Review-dec-2018](Review-dec-2018).</td>
</tr>
<tr class="odd">
<td>11-01-2019</td>
<td>Received updated v3.0 schematics from Creotech [Review-dec-2018](Review-dec-2018).</td>
</tr>
<tr class="even">
<td>23-01-2019</td>
<td>Kickstarted fmc-dac600m-12b-1cha-dds upgrade project with Creotech [dds-upgrade-meeting-notes](dds-upgrade-meeting-notes).</td>
</tr>
</tbody>
</table>
|**Date**|**Event**|
|----|----|
|01-04-2013|Specification written.|
|24-04-2013|Boards received and powered on, no smoke so far. One bug fixed (no 3.3V routed to the VCXO and PLL).|
|08-05-2013|[Proof-of-concept](https://www.ohwr.org/project/wr-d3s/wikis/RF-distribution-demo) VHDL and software.|
|20-11-2013|Specification of new version (v2) of the board including functionality of pulse generation with <50 ps RMS jitter and programmable fine delay.|
|22-11-2013|LNLS put order for the v2 design.|
|29-12-2013|Schematics of v2 at repository - ready for review.|
|20-01-2014|Reviewed schematics of v2: [Review-jan-2014](Review-jan-2014).|
|24-09-2014|V2 Design released in [EDMS](https://edms.cern.ch/nav/EDA-03010-V1-0).|
|15-01-2015|4 EDA-03010-V1-0 cards built and powered ([order](https://edh.cern.ch/Document/SupplyChain/DAI/5814761)).|
|24-08-2015|Production test system written. Not yet tested.|
|29-09-2015|PTS not yet tested. Some components need to be changed. Spurs on phase noise need investigation.|
|30-09-2015|Measured jitter 15 ps RMS. Goal is <2 ns. Should replace PLL + VCXO (500 MHz) by an AD9516, add test support logic (LDO type).|
|04-04-2016|5 EDA-03010-V1-0 cards with [modifications](https://edms.cern.ch/document/1577910/1) built and received ([order](https://edh.cern.ch/Document/SupplyChain/DAI/6279829)).|
|09-07-2018|Opening up project to investigate RF timing distribution over WR.|
|08-11-2018|Proposal to create a v3.0 to address some v2.0 issues.|
|28-11-2018|Received v3.0 schematics from Creotech [Review-dec-2018](Review-dec-2018).|
|14-12-2018|Schematic review v3.0 [Review-dec-2018](Review-dec-2018).|
|11-01-2019|Received updated v3.0 schematics from Creotech [Review-dec-2018](Review-dec-2018).|
|23-01-2019|Kickstarted fmc-dac600m-12b-1cha-dds upgrade project with Creotech [dds-upgrade-meeting-notes](dds-upgrade-meeting-notes).|
-----
......@@ -197,4 +135,4 @@ Rabbit](https://www.ohwr.org/project/white-rabbit/wiki) network.
### Files
* [fmc_dds.jpg](/uploads/c208dcd8224dcb830b6623615a92a2fa/fmc_dds.jpg)
* [fmc_dds_small.jpg](/uploads/e1c30619910ddb5a9158373b0bfcb0fb/fmc_dds_small.jpg)
\ No newline at end of file
* [fmc_dds_small.jpg](/uploads/e1c30619910ddb5a9158373b0bfcb0fb/fmc_dds_small.jpg)