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FMC ADC 500M 14b 4cha
Commit 4251f23d authored by Philipp Foedisch's avatar Philipp Foedisch
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PCB_ALTIUM/FMC_ADC500M.PrjPcb 0 → 100644
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PCB_ALTIUM/FMC_ADC500M.PrjPcbStructure 0 → 100644
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Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=ADC|SchDesignator=ADC|FileName=adc_ads54j54.SchDoc|SymbolType=Normal|RawFileName=adc_ads54j54.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
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Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=C|SchDesignator=C|FileName=analog_in.SchDoc|SymbolType=Normal|RawFileName=analog_in.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=Clocking|SchDesignator=Clocking|FileName=clocking.SchDoc|SymbolType=Normal|RawFileName=clocking.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=D|SchDesignator=D|FileName=analog_in.SchDoc|SymbolType=Normal|RawFileName=analog_in.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=FMC_HPC|SchDesignator=FMC_HPC|FileName=fmc_hpc_connections.SchDoc|SymbolType=Normal|RawFileName=fmc_hpc_connections.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=FMC_LPC|SchDesignator=FMC_LPC|FileName=fmc_lpc_connections.SchDoc|SymbolType=Normal|RawFileName=fmc_lpc_connections.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=FRONT_PANEL|SchDesignator=FRONT_PANEL|FileName=front_panel_connectors.SchDoc|SymbolType=Normal|RawFileName=front_panel_connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=LEDs_MISC|SchDesignator=LEDs_MISC|FileName=leds_misc.SchDoc|SymbolType=Normal|RawFileName=leds_misc.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=SINGLE_SUPPLY|SchDesignator=SINGLE_SUPPLY|FileName=power_single_supply.SchDoc|SymbolType=Normal|RawFileName=power_single_supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
Record=SheetSymbol|SourceDocument=top.SchDoc|Designator=SPLIT_SUPPLY|SchDesignator=SPLIT_SUPPLY|FileName=power_split_supply.SchDoc|SymbolType=Normal|RawFileName=power_split_supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID=
PCB_ALTIUM/adc_ads54j54.Harness 0 → 100644
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ADC_CONTROL=OVRA,OVRB,OVRC,OVRD,ENABLE,SCLK,SDATA,SDENb,SDOUT,SRESETb
JESD204B=SYSREFABP,SYSREFABM,SYSREFCDP,SYSREFCDM,SYNCbABP,SYNCbABM,SYNCbCDP,SYNCbCDM
MGT_PORTS_M2C_HPC=DP1_M2C_N,DP1_M2C_P,DP2_M2C_N,DP2_M2C_P,DP3_M2C_N,DP3_M2C_P,DP4_M2C_N,DP4_M2C_P,DP5_M2C_N,DP5_M2C_P,DP6_M2C_N,DP6_M2C_P,DP7_M2C_N,DP7_M2C_P
MGT_PORTS_M2C_LPC=DP0_M2C_N,DP0_M2C_P
PCB_ALTIUM/clocking.Harness 0 → 100644
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CLOCKING_CTRL=CS,SCLK,SDI,SDO,CLKRESET,LOLb,LOSb
SYSREF_INOUT=SYSREF_AB_P,SYSREF_AB_N,SYSREF_CD_P,SYSREF_CD_N,SYSREF_TO_FPGA_P,SYSREF_TO_FPGA_N,SYSREF_FROM_FPGA_P,SYSREF_FROM_FPGA_N,SYSREF_SEL
PCB_ALTIUM/fmc_hpc_connections.Harness 0 → 100644
View file @ 4251f23d
MGT_PORTS_M2C_HPC=DP1_M2C_N,DP1_M2C_P,DP2_M2C_N,DP2_M2C_P,DP3_M2C_N,DP3_M2C_P,DP4_M2C_N,DP4_M2C_P,DP5_M2C_N,DP5_M2C_P,DP6_M2C_N,DP6_M2C_P,DP7_M2C_N,DP7_M2C_P
PCB_ALTIUM/fmc_lpc_connections.Harness 0 → 100644
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LA_LPC=LA00_P_CC,LA00_N_CC,LA01_P_CC,LA01_N_CC,LA02_P,LA02_N,LA03_P,LA03_N,LA04_P,LA04_N,LA05_P,LA05_N,LA06_P,LA06_N,LA07_P,LA07_N,LA08_P,LA08_N,LA09_P,LA09_N,LA10_P,LA10_N,LA11_P,LA11_N,LA29_N,LA31_P,LA31_N,LA32_N,LA33_P,LA33_N
M2C_CLOCKS_LPC=CLK0_M2C_P,CLK0_M2C_N,CLK1_M2C_P,CLK1_M2C_N
MGT_CLOCKS_LPC=GBTCLK0_M2C_P,GBTCLK0_M2C_N
MGT_PORTS_M2C_LPC=DP0_M2C_P,DP0_M2C_N
PCB_ALTIUM/top.Harness 0 → 100644
View file @ 4251f23d
ADC_CONTROL=ENABLE,OVRA,OVRB,OVRC,OVRD,SCLK,SDATA,SDENb,SDOUT,SRESETb
CLOCKING_CTRL=CLKRESET,CS,LOLb,LOSb,SCLK,SDI,SDO
JESD204B=SYNCbABM,SYNCbABP,SYNCbCDM,SYNCbCDP,SYSREFABM,SYSREFABP,SYSREFCDM,SYSREFCDP
LA_LPC=LA00_N_CC,LA00_P_CC,LA01_N_CC,LA01_P_CC,LA02_N,LA02_P,LA03_N,LA03_P,LA04_N,LA04_P,LA05_N,LA05_P,LA06_N,LA06_P,LA07_N,LA07_P,LA08_N,LA08_P,LA09_N,LA09_P,LA10_N,LA10_P,LA11_N,LA11_P,LA29_N,LA31_P,LA31_N,LA32_N,LA33_P,LA33_N
M2C_CLOCKS_LPC=CLK0_M2C_N,CLK0_M2C_P,CLK1_M2C_N,CLK1_M2C_P
MGT_CLOCKS_LPC=GBTCLK0_M2C_N,GBTCLK0_M2C_P
SYSREF_INOUT=SYSREF_AB_N,SYSREF_AB_P,SYSREF_CD_N,SYSREF_CD_P,SYSREF_FROM_FPGA_N,SYSREF_FROM_FPGA_P,SYSREF_SEL,SYSREF_TO_FPGA_N,SYSREF_TO_FPGA_P
readme.md
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##FMC ADC 500M 14b 4cha
\ No newline at end of file
#FMC ADC 500M 14b 4cha
Directories:
- PCB_Altium: Altium Designer Project files
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