Commits · 352d33b719f6d7b6cb653f408a436efe346b3048 · Projects / FMC ADC 250M 16b 4cha

12 Aug, 2014 1 commit
- Added sch & pcb in pdf · 352d33b7
  Filip Świtakowski authored Aug 12, 2014
  
  352d33b7
28 Jun, 2014 1 commit
- rev 1.1 · 4d9b093d
  Grzegorz Kasprowicz authored Jun 28, 2014
```
clock mux bias
ADC LDO supply - 3.3 vs VADJ
balun bypass
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  4d9b093d
25 Jan, 2013 1 commit
- modified stackup slightly to fit to manufacturer's requirements · 84d50b72
  Grzegorz Kasprowicz authored Jan 25, 2013
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fixed some cosmetic bugs
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  84d50b72
24 Jan, 2013 1 commit

added machined FMC panel, added GND layer for better copper balancing on L3,… · a33508f4

Grzegorz Kasprowicz authored Jan 24, 2013

added machined FMC panel, added GND layer for better copper balancing on L3, added cutouts under SMA pins and input tracks, fixed silkscreen, fixed SMA connector layout - paste and soldermask opening was missing, did some cosmetic cleaning

a33508f4

07 Jan, 2013 1 commit
- fixed most of the issues - added 0R resistors for clock option selection, added silkscreen, logos. · 2d60aec1
  Grzegorz Kasprowicz authored Jan 07, 2013
  
  2d60aec1
14 Dec, 2012 1 commit
- fixed bugs in clock distribution, unified shield - same as in 130MHz FMC ADC · 7bee9c19
  Grzegorz Kasprowicz authored Dec 14, 2012
  
  7bee9c19
25 Nov, 2012 3 commits
- added OHWR license files to the directory · 97ce42b1
  Grzegorz Kasprowicz authored Nov 25, 2012
  
  97ce42b1
- added OHWR license info to the PCB · 8510c770
  Grzegorz Kasprowicz authored Nov 25, 2012
  
  8510c770
- added OHWR license note on each schematic · e3d7740b
  Grzegorz Kasprowicz authored Nov 25, 2012
  
  e3d7740b
23 Nov, 2012 1 commit
- added heatsink/shield · a15baeb5
  Grzegorz Kasprowicz authored Nov 23, 2012
  
  a15baeb5
22 Nov, 2012 1 commit
- final version, needed to be prepared for production · 3022414c
  Grzegorz Kasprowicz authored Nov 22, 2012
```
heatsink design needed as well
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  3022414c
21 Nov, 2012 1 commit
- routed. Cosmeting cleaning required. Still need to check some rules. · b2a13bd1
  Grzegorz Kasprowicz authored Nov 21, 2012
  
  b2a13bd1
20 Nov, 2012 1 commit
- almost done, some control tracks missing and cosmetic cleaning needed · 71dea831
  Grzegorz Kasprowicz authored Nov 20, 2012
  
  71dea831
19 Nov, 2012 1 commit

improved symmetry of the channels. · 6f1bd639

Grzegorz Kasprowicz authored Nov 19, 2012

Added die-casted shield + heatsink
fixed schematic bugs after review
added voltage level translator/buffer between FPGA and ADC
improved signal integrity of clock circuit

6f1bd639

14 Nov, 2012 1 commit
- improved symmetry between channels · c552b9a1
  Grzegorz Kasprowicz authored Nov 14, 2012
  
  c552b9a1
01 Oct, 2012 1 commit
- initial version of schematics, first placement of critical components · d59b8bf2
  Grzegorz Kasprowicz authored Oct 01, 2012
  
  d59b8bf2