Review02032010
Design review of FMCADC100M14b4cha
2 March 2010
Schematics of 2010-02-26 16:29.16
Present
Michael Sordet (BE/BI), Matthieu Cattin (BE/CO), Pablo Alvarez (BE/CO), Erik van der Bij (BE/CO), Maciej Fimiarz (designer, BE/CO)
General description of the design.
Maciej gave a general overview of the design. It is optmised for noise
levels, that's why low value resistors are used and the input impedance
is only 1 KOhm (or 50 Ohm selectable). The stability of the gain and
offset is mainly influenced by the MOS switches.
The anti-aliasing filter has it's -3dB point at 25 MHz, with a 4-pole
filter. The sampling frequency is programmable on the local oscillator,
or can be coming from the FMC carrier (production option), but it is
supposed to be 100 MHz.
The lowest sensitivity setting of the ADC (+/- 1V) is used for noise
reasons. But for this the differential ampifier in front should amplify
by a factor 2. It is not clear if this is better than having the highest
sensitivity setting of the ADC (+/- 0.5V) and have a unity gain
amplification in front.
Detailed comments on schematics
Sheet 1: High Pin Count Connector
- LA00_CC_P should be called LA00_P_CC (same for N). Change also where this signal is used.
- VIO_B_M2C is not used: remove signal.
- Remove all signals that are not used in the design to prevent confusion.
- Mark the meaning of B1-B4 and FIG1-FIG6.
- Mark LA23_N/P to be a differential pair.
- Check if LA06_P/N are correct (pair, both signals used?).
Sheet 2: Input stage
- Sheets 3, 4 and 5 should be the same. This has not been verified. Make sure all modifications are done on all channels.
- Consider inserting an inductor at the negative input to make it symmetrical to the positive input (verify AA's mail about this).
- Add a note on the input ranges, voltage ranges at critical points in the schematic. This should also make clear that it's an input range of 10V (Vpp) with a programmable offset between -5V and +5V. Possibly give examples of usage to clarify.
- If 50 Ohm setting: +/-7.5V maximum.
- Add names SW1-SW7 in schematic (refer to sheet 11).
Sheet 6: Linear Technologies' ADC
- Add a note about the different frequencies of DCO, FR, ENC.
- Add 2 resistors to select the sensitivity of the ADC (SENSE): 100 Ohm to Vdd, 100 K placeholder to Gnd (normally not mount).
- symbol misses overline on CS.
Sheet 7: DACs and Vref source
- Add comments on ranges of signals.
- Add 100nF on +12V_filtered of ADR445 (IC2).
- Add 100nF on supply of ADA4004 (IC5 DAC buffers).
- Check if the ADC can give out a status on the SDO pins. If so, connect it to the FMC connector.
- Use the B version of the reference voltage generator ADR445ARMZ. These have a better temperature stability (verify and verify price difference).
- EP (external pad) of the OPAMP should be connected to the negative supply voltage instead of the Gnd. Check with datasheet.
- The DACs are supplied with +6V while this is the absolute maximum voltage. Check if they should be supplied with a lower voltage and how it should be generated.
Sheet 8: I2C memory and LED indicator
- Redo the trigger input stage so that it can withstand a +/-10V input signal as users can by mistake connect an input signal to this connector.
- R117 56 Ohm trigger input termination resistor: use a 0.5 Watt type.
- Verify dissipation capability of R116.
- Change LEDs into green types.
- Add texts to LEDs: Trig'd, OK.
- Add thermometer IC. This can ultimately be used to add a temperature compensation. The same chip should also provide a unique serial ID.
- Verify if the memory is large enough to store all calibration parameters.
- Put the value of R118/R119 next to component.
- Document input levels and trigger level.
Sheet 9: Power supplies
- Add 10pF C to SET input of LT3080.
- Replace 60K4 SET resistor by 600K to have correct 6V output.
- Replace C46 1uF by at least 2.2uF.
- Symbols shutdown pins of IC9 and IC10 are not marked with active low marker.
- IC8 LT3080, pin EP should be connected to Vout and not to Gnd. Check datasheet.
- C48 (220pF on LT1931 output) should have a different value to match phase lead zero. Check datasheet.
Sheet 10: ADC clock generator
- Replace symbol by Si570 and re-verify with someone else.
- Add note on the I2C address.
Other comments
- Make a Bill-of-Material and verify if the number of different components can be reduced.
- Calculate the total component costs.
- Print out the netlist and verify it by hand to make absolutely sure that all signals are connected with the right number of pins.
- Add the datasheets of all used components in EDMS (Ordering info).
- Make sure that the capacitors are of the X7R type.
Additions to the manual
- Add a note about the crosstalk: do not put an input with a /-5V range next to one with a/-50mV range.
- Specify input ranges, maximum voltage with 50 Ohm setting, etc (see comments for Sheet 2).
PCB layout (preliminary review)
- Move IC8 12V to 6V drop-down converter to the other side of the FMC connector. This way it can be cooled by the stand-off pin (it dissipates 0.9 Watt).
- Consider placing the filter inductors alternatively on the top and bottom side to reduce coupling.
- Pay attention to ENC inputs of ADC: coupling capacitors should be very close to have no stubs.
- It seems that the LEDs and the connectors are too much advanced and will touch the front-panel.
- Use solid ground planes.
- Seriously consider to use power planes instead of using tracks.
- Verify the switching supply layout.
Conclusions
This has been a very useful review that revealed several serious mistakes and signalled other issues that will make the design more robust and that will improve its documentation. The changes will be implemented before finalising the PCB layout. We thank all people involved in the review.
- Erik van der Bij - 2 March 2010