Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha - Testing
Commits
ee79c2a4
Commit
ee79c2a4
authored
Mar 22, 2013
by
Matthieu Cattin
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fmc_adc: Add function to print trigger configuration.
parent
24a36d92
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
15 additions
and
0 deletions
+15
-0
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+15
-0
No files found.
test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
ee79c2a4
...
...
@@ -582,6 +582,21 @@ class CFmcAdc100m:
raise
FmcAdc100mOperationError
(
e
)
# Get trigger configuration
def
print_trig_config
(
self
):
#print("trig config: 0x%08X"%self.fmc_adc_csr.get_reg('TRIG_CFG'))
#print("trig delay: 0x%08X"%self.fmc_adc_csr.get_reg('TRIG_DLY'))
DIS_EN
=
[
'disable'
,
'enable'
]
HW_POL
=
[
'rising'
,
'falling'
]
HW_SEL
=
[
'internal'
,
'external'
]
hw_sel
=
self
.
fmc_adc_csr
.
get_field
(
'TRIG_CFG'
,
'HW_TRIG_SEL'
)
hw_pol
=
self
.
fmc_adc_csr
.
get_field
(
'TRIG_CFG'
,
'HW_TRIG_POL'
)
hw_en
=
self
.
fmc_adc_csr
.
get_field
(
'TRIG_CFG'
,
'HW_TRIG_EN'
)
sw_en
=
self
.
fmc_adc_csr
.
get_field
(
'TRIG_CFG'
,
'SW_TRIG_EN'
)
channel
=
self
.
fmc_adc_csr
.
get_field
(
'TRIG_CFG'
,
'INT_TRIG_SEL'
)
+
1
int_thres
=
self
.
fmc_adc_csr
.
get_field
(
'TRIG_CFG'
,
'INT_TRIG_THRES'
)
delay
=
self
.
fmc_adc_csr
.
get_reg
(
'TRIG_DLY'
)
print
(
"[FmcAdc100m] Trigger config => hw_en:
%
s, sw_en:
%
s, hw_sel:
%
s, hw_pol:
%
s, int_channel:
%
d, int_thres: 0x
%04
X, delay:
%
d"
%
(
DIS_EN
[
hw_en
],
DIS_EN
[
sw_en
],
HW_SEL
[
hw_sel
],
HW_POL
[
hw_pol
],
channel
,
int_thres
,
delay
))
# Internal trigger
def
set_int_trig
(
self
,
channel
,
polarity
,
threshold
):
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment