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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
24a36d92
Commit
24a36d92
authored
Mar 18, 2013
by
Matthieu Cattin
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test28: choose adc input params before awg params.
parent
c9145287
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test28.py
test/fmcadc100m14b4cha/python/test28.py
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test/fmcadc100m14b4cha/python/test28.py
View file @
24a36d92
...
...
@@ -86,8 +86,6 @@ ACQ_TIMEOUT = 10000 # ms
# Input waveform
SINE_MIN_FREQ
=
10E3
# Hz
SINE_MAX_FREQ
=
1E6
# Hz
SINE_MIN_AMPL
=
0.05
# Vpeak
SINE_MAX_AMPL
=
5.0
# Vpeak
# DMA
DMA_MAX_ITEMS
=
128
# items
...
...
@@ -300,7 +298,7 @@ def get_acq_data(carrier, fmc, samples, pre_trig_samples, nb_shots, in_range, ve
#######################################
#pre_trig_samples += 100
samples
+=
1000
#
samples += 1000
######################################
if
nb_shots
==
1
:
...
...
@@ -428,34 +426,60 @@ def main (default_directory='.'):
awg
=
Agilent33250A
(
device
=
awg_tty
[
0
],
bauds
=
AWG_BAUD
)
box
=
CCalibr_box
(
box_tty
[
0
])
fmc
.
testpat_dis
()
# Disable adc test pattern (just in case)
fmc
.
test_data_dis
()
# Disable test data to ddr (just in case)
########################################################################
# Clear DDR
########################################################################
t1
=
time
.
time
()
clear_ddr
(
carrier
,
True
)
t2
=
time
.
time
()
print
"elapsed time:
%.2
f seconds
\n
"
%
(
t2
-
t1
)
# Building input sine wave
sine_freq
=
SINE_MIN_FREQ
+
((
SINE_MAX_FREQ
-
SINE_MIN_FREQ
)
*
rdm
.
random
())
sine_ampl
=
SINE_MIN_AMPL
+
((
SINE_MAX_AMPL
-
SINE_MIN_AMPL
)
*
rdm
.
random
())
#sine_offset = (SINE_MAX_AMPL-sine_ampl)*rdm.random()
sine_offset
=
0
print
(
"Input sine wave => Frequency:
%3.3
fMHz, Amplitude:
%2.3
fVp, Offset:
%2.3
fV"
%
(
sine_freq
/
1E6
,
sine_ampl
,
sine_offset
))
# Configure AWG with sine wave
set_awg
(
awg
,
sine_freq
,
sine_ampl
,
sine_offset
,
True
)
########################################################################
# Set adc params
########################################################################
# Choose input termination randomly
adc_term
=
rdm
.
choice
([
'ON'
,
'OFF'
])
print
(
"Input termination:
%
s"
%
adc_term
)
# Find best input range given the sine wave amplitude
adc_range
=
get_best_input_range
(
sine_ampl
,
adc_term
,
True
)
# Choose input range randomly
adc_range
=
rdm
.
choice
([
'10V'
,
'1V'
,
'100mV'
])
print
(
"Input range:
%
s"
%
adc_range
)
# Configure ADC analogue input
set_adc_input
(
fmc
,
adc_term
,
adc_range
,
True
)
adc_offset
=
sine_offset
adc_offset
=
0
set_adc_offset
(
fmc
,
adc_offset
,
True
)
########################################################################
# Set awg params
########################################################################
# Building input sine wave
sine_freq
=
SINE_MIN_FREQ
+
((
SINE_MAX_FREQ
-
SINE_MIN_FREQ
)
*
rdm
.
random
())
sine_min_ampl
=
0.1
*
(
RANGES
[
adc_range
]
/
2
)
# 10% full scale
sine_max_ampl
=
0.9
*
(
RANGES
[
adc_range
]
/
2
)
# 90% full scale
if
adc_term
==
'ON'
:
sine_min_ampl
*=
2
sine_max_ampl
*=
2
sine_ampl
=
sine_min_ampl
+
((
sine_max_ampl
-
sine_min_ampl
)
*
rdm
.
random
())
#sine_offset = (sine_max_ampl-sine_ampl)*rdm.random()
sine_offset
=
0
print
(
"Input sine wave => Frequency:
%3.3
fMHz, Amplitude:
%2.3
fVp, Offset:
%2.3
fV"
%
(
sine_freq
/
1E6
,
sine_ampl
,
sine_offset
))
# Configure AWG with sine wave
set_awg
(
awg
,
sine_freq
,
sine_ampl
,
sine_offset
,
True
)
########################################################################
# Set acquisition params
########################################################################
# Configure trigger
trig_hw_sel
=
1
# external
trig_hw_pol
=
0
# rising
...
...
@@ -475,15 +499,15 @@ def main (default_directory='.'):
acq_samples
=
rdm
.
randrange
(
acq_min_samples
,
MULTISHOT_MAX_SIZE
+
1
)
acq_nb_shots
=
rdm
.
randrange
(
1
,
(
MEMORY_SIZE
/
acq_samples
)
+
1
)
else
:
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
# Can't use all available memory on-board.
# Bad memory management in my Python program...
#!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
#acq_samples = rdm.randrange(acq_min_samples, MEMORY_SIZE+1)
acq_samples
=
rdm
.
randrange
(
acq_min_samples
,
(
MEMORY_SIZE
/
4
)
+
1
)
acq_samples
=
rdm
.
randrange
(
acq_min_samples
,
(
MEMORY_SIZE
/
10
)
+
1
)
acq_nb_shots
=
1
print
(
"Final number of samples:
%
d"
%
acq_samples
)
#####################################
#acq_samples = 100000
#####################################
# Choose the trigger position randomly
acq_pre_trig_samples
=
rdm
.
randrange
(
0
,
acq_samples
+
1
)
acq_post_trig_samples
=
acq_samples
-
acq_pre_trig_samples
...
...
@@ -492,11 +516,21 @@ def main (default_directory='.'):
acq_decim_factor
=
1
set_acq
(
fmc
,
acq_nb_shots
,
acq_pre_trig_samples
,
acq_post_trig_samples
,
acq_decim_factor
,
True
)
########################################################################
# Set box params
########################################################################
# Connect AWG to one channel
channel
=
1
box
.
select_output_ch
(
channel
)
time
.
sleep
(
BOX_SET_SLEEP
)
########################################################################
# Make acqusisition
########################################################################
# Make acquisition
make_acq
(
fmc
,
True
)
...
...
@@ -505,33 +539,14 @@ def main (default_directory='.'):
print
(
"Number of retrieved samples:
%
d"
%
(
len
(
acq_data
)
/
4
))
# Plot data
plot_all
(
acq_data
,
max
(
acq_data
))
sys
.
exit
()
# Configuration
acq_config
(
fmc
)
error
=
0
# All inputs in calibration mode
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
fmc
.
set_input_range
(
i
,
"CAL"
)
# Disable test pattern (just in case)
fmc
.
testpat_dis
()
# Acquire and read channels
print
(
"Acquire and read all channels."
)
acq_data
=
acq_channels
(
fmc
,
carrier
)
print
(
"Read done."
)
acq_data_mean
=
acq_mean
(
acq_data
)
for
i
in
range
(
len
(
acq_data_mean
)):
print
"ADC channel
%
d mean value:
%
d"
%
(
i
+
1
,
acq_data_mean
[
i
])
# Reset offset DACs
fmc
.
dc_offset_reset
()
time
.
sleep
(
DAC_SET_SLEEP
)
...
...
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