Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha - Testing
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha - Testing
Commits
65ed453d
Commit
65ed453d
authored
Jul 12, 2013
by
Matthieu Cattin
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
fmc_adc_spec: Fix wrong wishbone module base addresses.
parent
d984b1cf
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
2 additions
and
2 deletions
+2
-2
fmc_adc_spec.py
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+2
-2
No files found.
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @
65ed453d
...
...
@@ -39,8 +39,8 @@ class CFmcAdc100mSpec:
GNUM_DMA_CSR_ADDR
=
0x1000
ONEWIRE_ADDR
=
0x1100
CSR_ADDR
=
0x1200
UTC_CORE_ADDR
=
0x
13
00
IRQ_CONTROLLER_ADDR
=
0x1
4
00
UTC_CORE_ADDR
=
0x
20
00
IRQ_CONTROLLER_ADDR
=
0x1
3
00
# Onewire core port
DS18B20_PORT
=
0
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment