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FMC ADC 100M 14b 4cha - Testing
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FMC ADC 100M 14b 4cha - Testing
Commits
d984b1cf
Commit
d984b1cf
authored
Jul 11, 2013
by
Matthieu Cattin
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fmc_adc: make the wishbone base addresses ready for multi-module.
parent
035f0419
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1 changed file
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14 additions
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13 deletions
+14
-13
fmc_adc.py
test/fmcadc100m14b4cha/python/fmc_adc.py
+14
-13
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test/fmcadc100m14b4cha/python/fmc_adc.py
View file @
d984b1cf
...
...
@@ -75,19 +75,19 @@ class FmcAdc100mOperationError(Exception):
class
CFmcAdc100m
:
FMC_SYS_I2C_ADDR
=
0x
3
000
FMC_SYS_I2C_ADDR
=
0x
1
000
EEPROM_ADDR
=
0x50
FMC_SPI_ADDR
=
0x
3
100
FMC_SPI_ADDR
=
0x
1
100
FMC_SPI_DIV
=
100
FMC_SPI_SS
=
{
'ADC'
:
0
,
'DAC1'
:
1
,
'DAC2'
:
2
,
'DAC3'
:
3
,
'DAC4'
:
4
}
FMC_I2C_ADDR
=
0x
3
200
FMC_I2C_ADDR
=
0x
1
200
SI570_ADDR
=
0x55
FMC_ONEWIRE_ADDR
=
0x
3
400
FMC_ONEWIRE_ADDR
=
0x
1
400
FMC_CSR_ADDR
=
0x
3
300
FMC_CSR_ADDR
=
0x
1
300
"""
...
...
@@ -202,21 +202,22 @@ class CFmcAdc100m:
return addr
"""
def
__init__
(
self
,
bus
):
def
__init__
(
self
,
bus
,
offset
=
0x4000
):
self
.
bus
=
bus
self
.
offset
=
offset
try
:
# Objects declaration
self
.
fmc_sys_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
FMC_SYS_I2C_ADDR
,
249
)
self
.
fmc_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
FMC_I2C_ADDR
,
249
)
self
.
fmc_sys_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
offset
+
self
.
FMC_SYS_I2C_ADDR
,
249
)
self
.
fmc_i2c
=
COpenCoresI2C
(
self
.
bus
,
self
.
offset
+
self
.
FMC_I2C_ADDR
,
249
)
self
.
eeprom_24aa64
=
C24AA64
(
self
.
fmc_sys_i2c
,
self
.
EEPROM_ADDR
)
self
.
si570
=
CSi57x
(
self
.
fmc_i2c
,
self
.
SI570_ADDR
)
self
.
eeprom_24aa64
=
C24AA64
(
self
.
fmc_sys_i2c
,
self
.
offset
+
self
.
EEPROM_ADDR
)
self
.
si570
=
CSi57x
(
self
.
fmc_i2c
,
self
.
offset
+
self
.
SI570_ADDR
)
self
.
fmc_onewire
=
COpenCoresOneWire
(
self
.
bus
,
self
.
FMC_ONEWIRE_ADDR
,
624
,
124
)
self
.
fmc_onewire
=
COpenCoresOneWire
(
self
.
bus
,
self
.
offset
+
self
.
FMC_ONEWIRE_ADDR
,
624
,
124
)
self
.
ds18b20
=
CDS18B20
(
self
.
fmc_onewire
,
0
)
self
.
fmc_spi
=
COpenCoresSPI
(
self
.
bus
,
self
.
FMC_SPI_ADDR
,
self
.
FMC_SPI_DIV
)
self
.
fmc_spi
=
COpenCoresSPI
(
self
.
bus
,
self
.
offset
+
self
.
FMC_SPI_ADDR
,
self
.
FMC_SPI_DIV
)
self
.
adc_cfg
=
CLTC217x
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'ADC'
])
self
.
dac_ch
=
[]
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC1'
]))
...
...
@@ -224,7 +225,7 @@ class CFmcAdc100m:
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC3'
]))
self
.
dac_ch
.
append
(
CMAX5442
(
self
.
fmc_spi
,
self
.
FMC_SPI_SS
[
'DAC4'
]))
self
.
fmc_adc_csr
=
CCSR
(
self
.
bus
,
self
.
FMC_CSR_ADDR
,
FMCADC100M_CSR
)
self
.
fmc_adc_csr
=
CCSR
(
self
.
bus
,
self
.
offset
+
self
.
FMC_CSR_ADDR
,
FMCADC100M_CSR
)
# Set channels gain to 1
self
.
fmc_adc_csr
.
set_field
(
'CH1_GAIN'
,
'VAL'
,
0x8000
)
...
...
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