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FMC ADC 100M 14b 4cha - Gateware
Commit e2122371 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[spec] meet timing by adjusting settings and multishot ram size

parent c3bee786
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Showing with 3 additions and 2 deletions
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @ e2122371
......@@ -120,7 +120,6 @@ INST "cmp_fmc_adc_mezzanine/*/cmp_ext_trig_sync/sync0" RLOC_ORIGIN = X30Y2
#----------------------------------------
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/clgen/clk_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_spi/*/Wrapped_SPI/shift/s_out" IOB = FALSE;
INST "cmp_fmc_adc_mezzanine/cmp_fmc_onewire/*/Wrapped_1wire/owr_oen_1" IOB = FALSE;
#----------------------------------------
# Clocks
......
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl
View file @ e2122371
......@@ -27,6 +27,8 @@ xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project set "Keep Hierarchy" "Yes"
xilinx::project save
xilinx::project close
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @ e2122371
......@@ -43,7 +43,7 @@ use work.wr_board_pkg.all;
entity spec_ref_fmc_adc_100Ms is
generic(
g_SIMULATION : integer := 0;
g_MULTISHOT_RAM_SIZE : natural := 4096;
g_MULTISHOT_RAM_SIZE : natural := 2048;
g_CALIB_SOFT_IP : string := "TRUE";
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram");
port
......
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