replace bit-bang onewire master with ds182x readout module (to access FMC UID+TEMP)

c3bee786 · Dimitris Lampridis · 2b23e6d5 · c3bee786 · c3bee786 · c3bee786
Commit c3bee786 authored Dec 10, 2019 by Dimitris Lampridis
5 changed files
--- a/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.cheby
@@ -30,11 +30,8 @@ memory-map:
    - submap:
        name: ds18b20_onewire_master
        address: 0x1700
-        size: 0x100
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
        description: DS18B20 OneWire master
+        filename: ../ip_cores/general-cores/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
    - submap:
        name: fmc_spi_master
        address: 0x1800

--- a/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
+++ b/hdl/cheby/fmc_adc_mezzanine_mmap.vhd
@@ -196,7 +196,7 @@ begin
  ds18b20_onewire_master_o.stb <= ds18b20_onewire_master_tr;
  ds18b20_onewire_master_wack <= ds18b20_onewire_master_i.ack and ds18b20_onewire_master_wt;
  ds18b20_onewire_master_rack <= ds18b20_onewire_master_i.ack and ds18b20_onewire_master_rt;
-  ds18b20_onewire_master_o.adr <= ((23 downto 0 => '0') & wb_i.adr(7 downto 2)) & (1 downto 0 => '0');
+  ds18b20_onewire_master_o.adr <= ((27 downto 0 => '0') & wb_i.adr(3 downto 2)) & (1 downto 0 => '0');
  ds18b20_onewire_master_o.sel <= (others => '1');
  ds18b20_onewire_master_o.we <= ds18b20_onewire_master_wt;
  ds18b20_onewire_master_o.dat <= wb_i.dat;

--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -171,10 +171,6 @@ architecture rtl of fmc_adc_mezzanine is
  signal si570_sda_out  : std_logic;
  signal si570_sda_oe_n : std_logic;

-  -- Mezzanine 1-wire
-  signal mezz_owr_en : std_logic_vector(0 downto 0);
-  signal mezz_owr_i  : std_logic_vector(0 downto 0);
-
  -- Interrupts (eic)
  signal ddr_wr_fifo_empty_d : std_logic;
  signal ddr_wr_fifo_empty_p : std_logic;
@@ -395,29 +391,17 @@ begin
  --    DS18B20 (thermometer + unique ID)
  ------------------------------------------------------------------------------

-  cmp_fmc_onewire : xwb_onewire_master
-    generic map(
-      g_interface_mode      => CLASSIC,
-      g_address_granularity => BYTE,
-      g_num_ports           => 1,
-      g_ow_btp_normal       => "5.0",
-      g_ow_btp_overdrive    => "1.0"
-      )
-    port map(
-      clk_sys_i => sys_clk_i,
+  cmp_fmc_onewine : entity work.xwb_ds182x_readout
+    generic map (
+      g_CLOCK_FREQ_KHZ   => 125000,
+      g_USE_INTERNAL_PPS => TRUE)
+    port map (
+      clk_i     => sys_clk_i,
      rst_n_i   => sys_rst_n_i,
-
-      slave_i => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE),
-      slave_o => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE),
-      desc_o  => open,
-
-      owr_pwren_o => open,
-      owr_en_o    => mezz_owr_en,
-      owr_i       => mezz_owr_i
-      );
-
-  mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
-  mezz_owr_i(0)   <= mezz_one_wire_b;
+      wb_i      => cnx_slave_in(c_WB_SLAVE_FMC_ONEWIRE),
+      wb_o      => cnx_slave_out(c_WB_SLAVE_FMC_ONEWIRE),
+      pps_p_i   => '0',
+      onewire_b => mezz_one_wire_b);

  ------------------------------------------------------------------------------
  -- FMC0 interrupt controller

--- a/hdl/testbench/include/fmc_adc_mezzanine_mmap.v
+++ b/hdl/testbench/include/fmc_adc_mezzanine_mmap.v
@@ -6,7 +6,7 @@
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER 'h1600
 `define FMC_ADC_MEZZANINE_MMAP_SI570_I2C_MASTER_SIZE 256
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 'h1700
-`define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 256
+`define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 'h1800
 `define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER_SIZE 32
 `define ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE 'h1900

--- a/software/include/hw/fmc_adc_mezzanine_mmap.h
+++ b/software/include/hw/fmc_adc_mezzanine_mmap.h
@@ -2,6 +2,7 @@
 #define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__

 #include "timetag_core_regs.h"
+#include "wb_ds182x_regs.h"
 #include "fmc_adc_100ms_csr.h"
 #define FMC_ADC_MEZZANINE_MMAP_SIZE 8192

@@ -19,7 +20,7 @@

 /* DS18B20 OneWire master */
 #define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER 0x1700UL
-#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 256
+#define FMC_ADC_MEZZANINE_MMAP_DS18B20_ONEWIRE_MASTER_SIZE 16

 /* Mezzanine SPI master (ADC control + DAC offsets) */
 #define FMC_ADC_MEZZANINE_MMAP_FMC_SPI_MASTER 0x1800UL
@@ -49,19 +50,22 @@ struct fmc_adc_mezzanine_mmap {
  uint32_t si570_i2c_master[64];

  /* [0x1700]: SUBMAP DS18B20 OneWire master */
-  uint32_t ds18b20_onewire_master[64];
+  struct wb_ds182x_regs ds18b20_onewire_master;
+
+  /* padding to: 1536 words */
+  uint32_t __padding_3[60];

  /* [0x1800]: SUBMAP Mezzanine SPI master (ADC control + DAC offsets) */
  uint32_t fmc_spi_master[8];

  /* padding to: 1600 words */
-  uint32_t __padding_3[56];
+  uint32_t __padding_4[56];

  /* [0x1900]: SUBMAP Timetag Core */
  struct timetag_core_regs timetag_core;

  /* padding to: 1600 words */
-  uint32_t __padding_4[416];
+  uint32_t __padding_5[416];
 };

 #endif /* __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__ */