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FMC ADC 100M 14b 4cha - Gateware
Commit ac96c3ad authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: update all dependencies and testbench 

In order to get latest releases and dma misaligment fix.
Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 3a6a3fa6
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ddr3-sp6-core @ 70f9de31
Subproject commit 28dad2087c8df45056179796c9337c149e3cec03
Subproject commit 70f9de318f155764fdd4b7e1ae7f9c5b77131930
general-cores @ 258eb8e0
Subproject commit 63f3671351127a398006e01f66b37adb7eda9a37
Subproject commit 258eb8e00f99f795fe9b98840b01ac4a8b92ec94
gn4124-core @ e7637624
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit e763762405dd5274d342285dbc64683221f1fb15
spec @ 1e9e50ec
Subproject commit 266a209cb945e7946c99ec01bace6990d08688bc
Subproject commit 1e9e50ecafc0584d42eb0ccd5682fb08ed32549d
svec @ 7d85d3b7
Subproject commit ce6b58a38c12da91494dafc2a77cce6f16c0762f
Subproject commit 7d85d3b7bcb88186cd49a8646053f67d3aceab41
vme64x-core @ f85c29db
Subproject commit 6abee52c1b5f3c2a40e202eb9f5890c05e0d7f66
Subproject commit f85c29dbca768bedd709b3f43448706c7d27b76d
wr-cores @ a72a4223
Subproject commit 3dcac4483417a159f0b9495adab0c15b7b45692b
Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ ac96c3ad
......@@ -301,18 +301,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal wb_ddr_fifo_full : std_logic;
signal wb_ddr_fifo_wr : std_logic;
signal wb_ddr_fifo_rd : std_logic;
signal wb_ddr_fifo_valid : std_logic;
signal wb_ddr_fifo_wr_en : std_logic;
-- RAM address counter
signal ram_addr_cnt : unsigned(24 downto 0);
signal ram_addr_cnt : unsigned(28 downto 0);
signal test_data_en : std_logic;
signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic;
-- Wishbone interface to DDR
signal wb_ddr_stall_t : std_logic;
-- IO from CSR registers
signal csr_regin : t_fmc_adc_100ms_csr_master_in;
signal csr_regout : t_fmc_adc_100ms_csr_master_out;
......@@ -1064,7 +1060,7 @@ begin
end if;
end process p_shots_cnt;
multishot_buffer_sel <= std_logic(shots_cnt(0));
multishot_buffer_sel <= not std_logic(shots_cnt(0));
shots_done <= '1' when shots_cnt = to_unsigned(1, shots_cnt'length) else '0';
remaining_shots <= std_logic_vector(shots_cnt);
......@@ -1366,7 +1362,7 @@ begin
p_dpram_addra_cnt : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_post_done <= (others => '0');
......@@ -1389,10 +1385,14 @@ begin
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data;
dpram1_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data;
dpram0_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '0' else '0';
dpram1_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '1' else '0';
dpram0_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram1_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram0_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '0' else '0';
dpram1_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '1' else '0';
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
......@@ -1453,10 +1453,9 @@ begin
p_dpram_addrb_cnt : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
dpram_addrb_cnt <= (others => '0');
dpram_valid_t <= '0';
dpram_valid <= '0';
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_valid_t <= '0';
dpram_valid <= '0';
else
if trig_tag_done = '1' then
dpram_addrb_cnt <= dpram_addra_trig - unsigned(pre_trig_value(c_DPRAM_DEPTH-1 downto 0));
......@@ -1483,7 +1482,7 @@ begin
generic map (
g_DATA_WIDTH => 65,
g_SIZE => 256,
g_SHOW_AHEAD => FALSE,
g_SHOW_AHEAD => TRUE,
g_WITH_EMPTY => TRUE,
g_WITH_FULL => TRUE,
g_WITH_ALMOST_EMPTY => FALSE,
......@@ -1509,15 +1508,15 @@ begin
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
p_wb_ddr_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
if (wb_ddr_fifo_empty = '1') then
wb_ddr_fifo_valid <= '0';
end if;
end if;
end process;
-- p_wb_ddr_fifo_valid : process (sys_clk_i) is
-- begin
-- if rising_edge(sys_clk_i) then
-- wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
-- if (wb_ddr_fifo_empty = '1') then
-- wb_ddr_fifo_valid <= '0';
-- end if;
-- end if;
-- end process;
p_wb_ddr_fifo_input : process (sys_clk_i)
begin
......@@ -1544,11 +1543,13 @@ begin
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_stall_t);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_master_i.stall);
------------------------------------------------------------------------------
-- RAM address counter (32-bit word address)
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
-- RAM address counter (64-bit word address)
p_ram_addr_cnt : process (wb_ddr_clk_i)
begin
if rising_edge(wb_ddr_clk_i) then
......@@ -1557,70 +1558,81 @@ begin
else
if acq_start = '1' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_valid = '1' then
elsif wb_ddr_fifo_empty = '0' and wb_ddr_master_i.stall = '0' then
ram_addr_cnt <= ram_addr_cnt + 1;
end if;
end if;
end if;
end process p_ram_addr_cnt;
------------------------------------------------------------------------------
with acq_fsm_state select
wb_ddr_master_o.cyc <=
dpram_valid or not wb_ddr_fifo_empty when "001",
'1' when others;
wb_ddr_master_o.stb <= not wb_ddr_fifo_empty;
-- Convert to 32-bit word addressing for Wishbone
wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0";
wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF";
with test_data_en select
wb_ddr_master_o.dat <=
x"00000000" & "000" & std_logic_vector(ram_addr_cnt) when '1',
wb_ddr_fifo_dout(63 downto 0) when others;
-- Store trigger DDR address (byte address)
------------------------------------------------------------------------------
p_trig_addr : process (wb_ddr_clk_i)
begin
if rising_edge(wb_ddr_clk_i) then
if wb_ddr_rst_n_i = '0' then
trig_addr <= (others => '0');
else
if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_valid = '1' then
trig_addr <= "0000" & std_logic_vector(ram_addr_cnt) & "000";
if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_empty = '0' then
-- Convert to byte addressing
trig_addr <= std_logic_vector(ram_addr_cnt) & "000";
end if;
end if;
end if;
end process p_trig_addr;
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (wb_ddr_clk_i)
begin
if rising_edge(wb_ddr_clk_i) then
if wb_ddr_rst_n_i = '0' then
wb_ddr_master_o.cyc <= '0';
wb_ddr_master_o.we <= '0';
wb_ddr_master_o.stb <= '0';
wb_ddr_master_o.adr <= (others => '0');
wb_ddr_master_o.dat <= (others => '0');
wb_ddr_stall_t <= '0';
else
if wb_ddr_fifo_valid = '1' then
wb_ddr_master_o.stb <= '1';
wb_ddr_master_o.adr <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_master_o.dat <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
else
wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
end if;
else
wb_ddr_master_o.stb <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_master_o.cyc <= '1';
wb_ddr_master_o.we <= '1';
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_master_o.cyc <= '0';
wb_ddr_master_o.we <= '0';
end if;
wb_ddr_stall_t <= wb_ddr_master_i.stall;
-- p_wb_master : process (wb_ddr_clk_i)
-- begin
-- if rising_edge(wb_ddr_clk_i) then
-- if wb_ddr_rst_n_i = '0' then
-- wb_ddr_master_o.cyc <= '0';
-- wb_ddr_master_o.we <= '0';
-- wb_ddr_master_o.stb <= '0';
-- wb_ddr_master_o.adr <= (others => '0');
-- wb_ddr_master_o.dat <= (others => '0');
-- wb_ddr_stall_t <= '0';
-- else
-- if wb_ddr_fifo_valid = '1' then
-- wb_ddr_master_o.stb <= '1';
-- wb_ddr_master_o.adr <= "0000000" & std_logic_vector(ram_addr_cnt);
-- if test_data_en = '1' then
-- wb_ddr_master_o.dat <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
-- else
-- wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
-- end if;
-- else
-- wb_ddr_master_o.stb <= '0';
-- end if;
-- if wb_ddr_fifo_valid = '1' then
-- wb_ddr_master_o.cyc <= '1';
-- wb_ddr_master_o.we <= '1';
-- elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
-- wb_ddr_master_o.cyc <= '0';
-- wb_ddr_master_o.we <= '0';
-- end if;
-- wb_ddr_stall_t <= wb_ddr_master_i.stall;
-- end if;
-- end if;
-- end process p_wb_master;
end if;
end if;
end process p_wb_master;
wb_ddr_master_o.sel <= X"FF";
-- Trigout
......
hdl/testbench/spec_ref_design/.gitignore 0 → 100644
View file @ ac96c3ad
Makefile
work/
transcript
vsim.wlf
NullFile
modelsim.ini
buildinfo_pkg.vhd
hdl/testbench/spec_ref_design/Manifest.py 0 → 100644
View file @ ac96c3ad
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
include_dirs = [
"../include",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim/",
fetchto + "/general-cores/modules/wishbone/wb_spi/",
fetchto + "/ddr3-sp6-core/hdl/sim/",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/spec_ref_design",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_64b_32b" ]
hdl/testbench/spec_ref_design/main.sv 0 → 100644
View file @ ac96c3ad
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
`include "spec_ref_fmc_adc_100Ms_mmap.v"
`include "fmc_adc_mezzanine_mmap.v"
`include "fmc_adc_100Ms_csr.v"
`include "fmc_adc_eic_regs.v"
`include "timetag_core_regs.v"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
`define ADC_OFFSET `ADDR_SPEC_REF_FMC_ADC_100M_MMAP_FMC_ADC_MEZZANINE
`define CSR_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_100M_CSR
`define EIC_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_FMC_ADC_EIC
`define TAG_BASE `ADC_OFFSET + `ADDR_FMC_ADC_MEZZANINE_MMAP_TIMETAG_CORE
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
IGN4124PCIMaster i_gn4124 ();
reg adc_dco = 1'b0;
reg adc_fr = 1'b0;
reg ext_trig = 1'b0;
reg adc_data_dir = 1'b0;
reg[3:0] adc_dat_odd = 4'h0;
reg[3:0] adc_dat_even = 4'h0;
reg signed [13:0] adc_data = 0;
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
pulldown(ddr_rzq);
// 400Mhz
always #1.25ns adc_dco <= ~adc_dco;
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
bit [4:0] slot_id = 8;
spec_ref_fmc_adc_100Ms
#(
.g_SIMULATION(1)
)
DUT
(
.button1_n_i (rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_125m_gtp_p_i (clk_125m_pllref),
.clk_125m_gtp_n_i (~clk_125m_pllref),
.adc_ext_trigger_p_i (ext_trig),
.adc_ext_trigger_n_i (~ext_trig),
.adc_dco_p_i (adc_dco),
.adc_dco_n_i (~adc_dco),
.adc_fr_p_i (~adc_fr),
.adc_fr_n_i (adc_fr),
.adc_outa_p_i (adc_dat_odd),
.adc_outa_n_i (~adc_dat_odd),
.adc_outb_p_i (adc_dat_even),
.adc_outb_n_i (~adc_dat_even),
.gn_rst_n_i (i_gn4124.rst_n),
.gn_p2l_clk_n_i (i_gn4124.p2l_clk_n),
.gn_p2l_clk_p_i (i_gn4124.p2l_clk_p),
.gn_p2l_rdy_o (i_gn4124.p2l_rdy),
.gn_p2l_dframe_i (i_gn4124.p2l_dframe),
.gn_p2l_valid_i (i_gn4124.p2l_valid),
.gn_p2l_data_i (i_gn4124.p2l_data),
.gn_p_wr_req_i (i_gn4124.p_wr_req),
.gn_p_wr_rdy_o (i_gn4124.p_wr_rdy),
.gn_rx_error_o (i_gn4124.rx_error),
.gn_l2p_clk_n_o (i_gn4124.l2p_clk_n),
.gn_l2p_clk_p_o (i_gn4124.l2p_clk_p),
.gn_l2p_dframe_o (i_gn4124.l2p_dframe),
.gn_l2p_valid_o (i_gn4124.l2p_valid),
.gn_l2p_edb_o (i_gn4124.l2p_edb),
.gn_l2p_data_o (i_gn4124.l2p_data),
.gn_l2p_rdy_i (i_gn4124.l2p_rdy),
.gn_l_wr_rdy_i (i_gn4124.l_wr_rdy),
.gn_p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b (),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n)
);
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr0
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
int adc_div = 0;
always@(negedge adc_dco)
begin
#625ps;
if(adc_div == 1) begin
adc_fr <= ~adc_fr;
adc_div <= 0;
end
else begin
adc_div <= adc_div + 1;
end
end
// Generate a triangular waveform on all channels.
always@(posedge adc_fr)
begin
if ((adc_data > 400) || (adc_data < -400)) begin
adc_data_dir = ~adc_data_dir;
end
if (adc_data_dir == 0) begin
adc_data = adc_data + 8;
end
else begin
adc_data = adc_data - 8;
end
adc_dat_odd = {4{adc_data[13]}};
adc_dat_even = {4{adc_data[12]}};
#1250ps;
adc_dat_odd = {4{adc_data[11]}};
adc_dat_even = {4{adc_data[10]}};
#1250ps;
adc_dat_odd = {4{adc_data[9]}};
adc_dat_even = {4{adc_data[8]}};
#1250ps;
adc_dat_odd = {4{adc_data[7]}};
adc_dat_even = {4{adc_data[6]}};
#1250ps;
adc_dat_odd = {4{adc_data[5]}};
adc_dat_even = {4{adc_data[4]}};
#1250ps;
adc_dat_odd = {4{adc_data[3]}};
adc_dat_even = {4{adc_data[2]}};
#1250ps;
adc_dat_odd = {4{adc_data[1]}};
adc_dat_even = {4{adc_data[0]}};
#1250ps;
adc_dat_odd = {4{1'b0}};
adc_dat_even = {4{1'b0}};
end
task adc_status_print (input uint64_t val);
string msg;
msg = $sformatf ("<%t> ADC STATUS: FSM_STATE=%0d, PLL_LOCKED=%0d, PLL_SYNCED=%0d, CFG_OK=%0d",
$realtime,
(val & `FMC_ADC_100MS_CSR_STA_FSM) >> `FMC_ADC_100MS_CSR_STA_FSM_OFFSET,
(val & `FMC_ADC_100MS_CSR_STA_SERDES_PLL) >> `FMC_ADC_100MS_CSR_STA_SERDES_PLL_OFFSET,
(val & `FMC_ADC_100MS_CSR_STA_SERDES_SYNCED) >> `FMC_ADC_100MS_CSR_STA_SERDES_SYNCED_OFFSET,
(val & `FMC_ADC_100MS_CSR_STA_ACQ_CFG) >> `FMC_ADC_100MS_CSR_STA_ACQ_CFG_OFFSET);
$display(msg);
endtask // adc_status_print
initial begin
int i;
uint64_t val, expected;
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
$timeformat (-6, 3, "us", 10);
#2us;
expected = 'h19;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
begin
adc_status_print(val);
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
end
// Configure the EIC for an interrupt on ACQ_END
acc.write(`EIC_BASE + `ADDR_FMC_ADC_EIC_REGS_IER, 'h2);
// Configure the VIC
acc.write(`VIC_BASE + 'h8, 'h7f);
acc.write(`VIC_BASE + 'h0, 'h1);
// FMC-ADC core general configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000001);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
// FMC-ADC core channel configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_CALIB, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
// FMC-ADC core trigger configuration
val = (16'h100 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET) |
(16'h300 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES, val);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
begin
adc_status_print(val);
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
end
#1us;
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER, 'h00000032);
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_SECONDS_LOWER, 'h00005a34);
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_COARSE, 'h00000000);
$display("<%t> START ACQ 1/4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#200ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFF); // soft trigger
wait (DUT.cmp_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("<%t> END ACQ 1/4", $realtime);
acc.write(`EIC_BASE + `ADDR_FMC_ADC_EIC_REGS_ISR, 'h2);
acc.write(`VIC_BASE + 'h1c, 'h0);
#200ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000003); // #nshots: 3x multi-shot acq
$display("<%t> START ACQ 2/4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#500ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFE); // soft trigger
#500ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFD); // soft trigger
#500ns;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFC); // soft trigger
wait (DUT.cmp_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("<%t> END ACQ 2/4", $realtime);
acc.write(`EIC_BASE + `ADDR_FMC_ADC_EIC_REGS_ISR, 'h2);
acc.write(`VIC_BASE + 'h1c, 'h0);
#1us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000005);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
$display("<%t> START ACQ 3/4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
wait (DUT.cmp_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("<%t> END ACQ 3/4", $realtime);
acc.write(`EIC_BASE + `ADDR_FMC_ADC_EIC_REGS_ISR, 'h2);
acc.write(`VIC_BASE + 'h1c, 'h0);
#1us;
// set time trigger
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_UPPER, 'h00000032);
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_TIME_TRIG_SECONDS_LOWER, 'h00005a34);
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_TIME_TRIG_COARSE, 'h00001100);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h000001fd);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000001);
$display("<%t> START ACQ 4/4", $realtime);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#5us;
wait (DUT.cmp_fmc_adc_mezzanine.acq_end_irq_o == 1);
$display("<%t> END ACQ 4/4", $realtime);
acc.write(`EIC_BASE + `ADDR_FMC_ADC_EIC_REGS_ISR, 'h2);
acc.write(`VIC_BASE + 'h1c, 'h0);
#1us;
expected = 'h39;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
begin
adc_status_print(val);
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
end
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_POS, val);
$display("<%t> Start DMA, trigger position in DDR: %.8x", $realtime, val);
// DMA transfer
acc.write(`DMA_BASE + 'h08, val); // dma start addr
acc.write(`DMA_BASE + 'h0C, 'h00001000); // host addr
acc.write(`DMA_BASE + 'h10, 'h00000000);
// length = (samples + trigger sample + 2 for tag) * 8 bytes
acc.write(`DMA_BASE + 'h14, 'h00001000); // length
acc.write(`DMA_BASE + 'h18, 'h00000000); // next
acc.write(`DMA_BASE + 'h1C, 'h00000000);
acc.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
acc.write(`DMA_BASE + 'h00, 'h00000001); // xfer start
wait (DUT.inst_spec_base.irqs[2] == 1);
$display("<%t> END DMA", $realtime);
acc.write(`DMA_BASE + 'h04, 'h04); // clear DMA IRQ
acc.write(`VIC_BASE + 'h1c, 'h0);
$display ("Simulation PASSED");
$finish;
end
initial begin
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.inst_spec_base.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.inst_spec_base.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.inst_spec_base.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
endmodule // main
hdl/testbench/spec_ref_design/run.do 0 → 100644
View file @ ac96c3ad
vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
hdl/testbench/spec_ref_design/run_ci.do 0 → 100644
View file @ ac96c3ad
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run -all
hdl/testbench/spec_ref_design/wave.do 0 → 100644
View file @ ac96c3ad
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/acq_in_trig_tag
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/trig_addr
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_full
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_empty
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -group {SYNC FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -group {DDR FIFO} /main/DUT/cmp_fmc_adc_mezzanine/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -group DDR_WB0 /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/rst_n_i
add wave -noupdate -group DDR_WB0 /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_clk_i
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_cyc_i
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_stb_i
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_stb_valid
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_addr_i
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_sel_i
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_stall_o
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_ack_o
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_data_o
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_we_i
add wave -noupdate -group DDR_WB0 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/wb_data_i
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/cmd_fsm_state
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_stall
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_bl_o
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_burst_cnt
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_byte_addr_o
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_instr_o
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_empty_i
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_en_o
add wave -noupdate -group DDR_WB0 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_cmd_full_i
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_count_i
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_data_i
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_empty_i
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_en_o
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_error_i
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_full_i
add wave -noupdate -group DDR_WB0 -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_rd_overflow_i
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_en_o
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_mask_o
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_data_o
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_full_i
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_empty_i
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_count_i
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_underrun_i
add wave -noupdate -group DDR_WB0 -expand -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/ddr_wr_error_i
add wave -noupdate -expand -group DDR_WB1 /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/rst_n_i
add wave -noupdate -expand -group DDR_WB1 /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_clk_i
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_cyc_i
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stb_i
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stb_valid
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_sel_i
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_ack_o
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_we_i
add wave -noupdate -expand -group DDR_WB1 -expand -group Wishbone -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/cmd_fsm_state
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_stall
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate -expand -group DDR_WB1 -expand -group {CMD port} -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i
add wave -noupdate -expand -group DDR_WB1 -expand -group {RD port} -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_en_o
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_o
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_data_o
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i
add wave -noupdate -expand -group DDR_WB1 -group {WR port} /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_error_i
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/clk_i
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_req_o
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_dframe_o
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_64b_address
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/l2p_dma_current_state
add wave -noupdate -color Coral /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_full
add wave -noupdate -color Coral /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_empty
add wave -noupdate -color Coral /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -color Coral /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/data_fifo_dout
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_valid_o
add wave -noupdate /main/DUT/inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma/cmp_l2p_dma_master/ldm_arb_data_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {49697641190 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 366
configure wave -valuecolwidth 182
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 400000
configure wave -gridperiod 800000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {52312050 ps}
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