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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
238666a4
Commit
238666a4
authored
Oct 31, 2019
by
Dimitris Lampridis
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initial port of SPEC REF to the Convention
parent
d98dbd10
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11 changed files
with
234 additions
and
985 deletions
+234
-985
.gitmodules
.gitmodules
+3
-0
ddr3-sp6-core
hdl/ip_cores/ddr3-sp6-core
+1
-1
general-cores
hdl/ip_cores/general-cores
+1
-1
gn4124-core
hdl/ip_cores/gn4124-core
+1
-1
spec
hdl/ip_cores/spec
+1
-0
fmc_adc_mezzanine.vhd
hdl/rtl/fmc_adc_mezzanine.vhd
+6
-25
fmc_adc_mezzanine_pkg.vhd
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
+0
-3
Manifest.py
hdl/syn/spec_ref_design_wr/Manifest.py
+15
-14
spec_ref_fmc_adc_100Ms_wr.ucf
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
+27
-398
Manifest.py
hdl/top/spec_ref_design/Manifest.py
+9
-0
spec_ref_fmc_adc_100Ms.vhd
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
+170
-542
No files found.
.gitmodules
View file @
238666a4
...
...
@@ -13,3 +13,6 @@
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
ddr3-sp6-core
@
1a129390
Subproject commit
bb5b8f75e6f85335b43fef320375404686a74008
Subproject commit
1a1293900e6334bc41251ee84d0ae7d19980e584
general-cores
@
be61ce73
Subproject commit
eaacde903ef842af456c867947a0f1005f8bb4f3
Subproject commit
be61ce73a43d0231e8edc2f12133b918e3d1c9e4
gn4124-core
@
91d5efac
Subproject commit
72adf76dab9a6fc33fbff7c86d786c31e175a46a
Subproject commit
91d5eface7608d306991d2c1aa4e6f5210e9305c
spec
@
531dec91
Subproject commit 531dec9158aa05caa7aa10f91306999a39f3b1ef
hdl/rtl/fmc_adc_mezzanine.vhd
View file @
238666a4
...
...
@@ -119,9 +119,6 @@ entity fmc_adc_mezzanine is
mezz_one_wire_b
:
inout
std_logic
;
-- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
;
-- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i
:
in
std_logic
;
-- WR link status bit
wr_tm_time_valid_i
:
in
std_logic
;
-- WR timecode valid status bit
wr_tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
-- WR timecode seconds
...
...
@@ -234,14 +231,6 @@ architecture rtl of fmc_adc_mezzanine is
signal
wb_csr_out
:
t_wishbone_slave_in
;
signal
wb_csr_in
:
t_wishbone_slave_out
;
-- Mezzanine system I2C for EEPROM
signal
sys_scl_in
:
std_logic
;
signal
sys_scl_out
:
std_logic
;
signal
sys_scl_oe_n
:
std_logic
;
signal
sys_sda_in
:
std_logic
;
signal
sys_sda_out
:
std_logic
;
signal
sys_sda_oe_n
:
std_logic
;
-- Mezzanine SPI
signal
spi_din_t
:
std_logic_vector
(
3
downto
0
)
:
=
(
others
=>
'0'
);
signal
spi_ss_t
:
std_logic_vector
(
7
downto
0
);
...
...
@@ -349,20 +338,12 @@ begin
slave_o
=>
cnx_slave_out
(
c_WB_SLAVE_FMC_SYS_I2C
),
desc_o
=>
open
,
scl_pad_i
(
0
)
=>
sys_scl_in
,
scl_pad_o
(
0
)
=>
sys_scl_out
,
scl_padoen_o
(
0
)
=>
sys_scl_oe_n
,
sda_pad_i
(
0
)
=>
sys_sda_in
,
sda_pad_o
(
0
)
=>
sys_sda_out
,
sda_padoen_o
(
0
)
=>
sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
sys_scl_b
<=
sys_scl_out
when
sys_scl_oe_n
=
'0'
else
'Z'
;
sys_scl_in
<=
sys_scl_b
;
sys_sda_b
<=
sys_sda_out
when
sys_sda_oe_n
=
'0'
else
'Z'
;
sys_sda_in
<=
sys_sda_b
;
scl_pad_i
(
0
)
=>
'1'
,
scl_pad_o
(
0
)
=>
open
,
scl_padoen_o
(
0
)
=>
open
,
sda_pad_i
(
0
)
=>
'1'
,
sda_pad_o
(
0
)
=>
open
,
sda_padoen_o
(
0
)
=>
open
);
------------------------------------------------------------------------------
-- Mezzanine SPI master
...
...
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @
238666a4
...
...
@@ -124,9 +124,6 @@ package fmc_adc_mezzanine_pkg is
mezz_one_wire_b
:
inout
std_logic
;
-- Mezzanine 1-wire interface (DS18B20 thermometer + unique ID)
sys_scl_b
:
inout
std_logic
;
-- Mezzanine system I2C clock (EEPROM)
sys_sda_b
:
inout
std_logic
;
-- Mezzanine system I2C data (EEPROM)
wr_tm_link_up_i
:
in
std_logic
;
-- WR link status bit
wr_tm_time_valid_i
:
in
std_logic
;
-- WR timecode valid status bit
wr_tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
-- WR timecode seconds
...
...
hdl/syn/spec_ref_design_wr/Manifest.py
View file @
238666a4
...
...
@@ -9,29 +9,30 @@ syn_top = "spec_ref_fmc_adc_100Ms"
syn_project
=
syn_top
+
"_wr.xise"
syn_tool
=
"ise"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../ip_cores"
files
=
[
syn_top
+
"_wr.ucf"
,
"buildinfo_pkg.vhd"
,
]
modules
=
{
"local"
:
[
"../../top/spec_ref_design"
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git"
,
"git://ohwr.org/hdl-core-lib/gn4124-core.git"
,
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
],
}
fetchto
=
"../../ip_cores"
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
ctrls
=
[
"bank3_64b_32b"
]
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
syn_post_project_cmd
=
(
"$(TCL_INTERPRETER) "
+
\
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
\
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
spec_base_ucf
=
[
'wr'
,
'ddr3'
,
'onewire'
,
'spi'
]
ctrls
=
[
"bank3_64b_32b"
]
hdl/syn/spec_ref_design_wr/spec_ref_fmc_adc_100Ms_wr.ucf
View file @
238666a4
This diff is collapsed.
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hdl/top/spec_ref_design/Manifest.py
View file @
238666a4
...
...
@@ -4,8 +4,17 @@ files = [
"dma_eic.vhd"
,
]
fetchto
=
"../../ip_cores"
modules
=
{
"local"
:
[
"../../../"
,
],
"git"
:
[
"https://ohwr.org/project/general-cores.git"
,
"https://ohwr.org/project/wr-cores.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
"https://ohwr.org/project/gn4124-core.git"
,
"https://ohwr.org/project/spec.git"
,
],
}
hdl/top/spec_ref_design/spec_ref_fmc_adc_100Ms.vhd
View file @
238666a4
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