Hardware design notes
All notes are with reference to the V3 design.
System on Chip (SoC)
A Xilinx Zynq 7000 (XC7Z030) has been chosen, where the main criteria was the package and user pins available to the PL (i.e. the FPGA part) because both FMC slots needed all pins connected. To make this work, the Vadj voltages of the slots had to be fixed as follows: slot-1 to 2.5V and slot-2 to 1.8V. This has an impact on the possible FMCs that can be used, one should check the Vadj they support! The FMCs produced at CERN support in general only a Vadj of 2.5V.
Ethernet PHY
IC8
a Microchip KSZ8794, a 4-Port 10/100 Managed Ethernet Switch with Gigabit Uplink, has been selected for this design. Only late in the design process it was found that there's no Linux kernel mainline support (e.g. DSA) and even the generic PHY driver only works after applying a custom patch, see the OE meta-user layer sources.
The PHY has two interfaces to its device registers, MIIM and SPI. The linux kernel has standard support for MIIM which works (e.g. to get link status), however all advanced switch configuration registers can only be accessed through the SPI interface. The design here has by default the MDIO pins wired to the SoC bank-501 to be used by the PS (i.e. the SoC ARM CPUs). To make full use of the switch functionality however, all SPI-inteface pins have been wired to the PL. Note that the nets MKDI_CLK
and MDIO_IO
are used by both interfaces and require a connection to a high-impedance IOB in the gateware when using MIIM. To use the SPI interface, the following should be done:
- remove
SPIQ
pull-upR36
- add
SPIQ
pull-downR400
- instantiate a SPI driver in the PL This has been tested and works, however the linux kernel lacks a full KSZ8794 DSA driver.