Hardware design notes
All notes are with reference to the V3 design.
System on Chip (SoC)
A Xilinx Zynq 7000 (XC7Z030) has been chosen, where the main criteria was the package and user pins available to the PL (i.e. the FPGA part) because both FMC slots needed all pins connected. To make this work, the Vadj voltages of the slots had to be fixed as follows: slot-1 to 2.5V and slot-2 to 1.8V. This has an impact on the possible FMCs that can be used, one should check the Vadj they support! The FMCs produced at CERN support in general only a Vadj of 2.5V.
Ethernet PHY
IC8
a Microchip KSZ8794, a 4-Port 10/100 Managed Ethernet Switch with Gigabit Uplink, has been selected for this design. Only late in the design process it was found that there's no Linux kernel mainline support (e.g. DSA) and even the generic PHY driver only works after applying a custom patch, see the OE meta-user layer sources. This custom patch forces the driver to assign a fixed speed of 1G between the SoC MAC and PHY Port-4, no-matter the actual speed detected when the link on ETH2 port comes up.
The PHY has two interfaces to its device registers, MIIM and SPI. The linux kernel has standard support for MIIM which works (e.g. to get link status), however all advanced switch configuration registers can only be accessed through the SPI interface. The design here has by default the MDIO pins wired to the SoC bank-501 to be used by the PS (i.e. the SoC ARM CPUs). To make full use of the switch functionality however, all SPI-inteface pins have been wired to the PL. Note that the nets MKDI_CLK
and MDIO_IO
are used by both interfaces and require a connection to a high-impedance IOB in the gateware when using MIIM. To use the SPI interface, the following should be done:
- remove
SPIQ
pull-upR36
- add
SPIQ
pull-downR400
- instantiate a SPI driver in the PL
The interface has been tested and works, however the linux kernel lacks a full KSZ8794 DSA driver.
Reset SoC on PHY Magic Package receipt
The purpose of the PHY_PME_N
net, which connects IC8 PME_N pin
to a SN74LVC1G17DBVR Schmitt trigger and IC44
monostable, is to reset the SoC when a Magic Packet is received over Ethernet. To implement this functionality however, the PHY needs to be configured as such over the SPI interface. This has never been tested.
USB 3.0 A connector for high speed serial link
This USB connector, J22
, is not wired to an USB peripheral but to the SoC bank-0 GTX gigabit transceivers. The idea is to use a COTS USB crossed cable to implement a fast serial link between two cards.
Power Delivery Network PDN
Power Controller UCD90120A and regulator sequencing
This device, IC34
, is a 12-Channel Sequencer and System Health Monitor and has been selected to facilitate the sequencing requirements of the Zynq SoC. It is monitoring several critical power supply voltages and currents through its MON*
inputs, and enabling these by driving the regulators enable
pins through its GPIO*
outputs. Its serial PMBus interface is wired to the SoC which can supervise and command the regulators. An existing linux mainline driver makes this effortless. The power sequencing is described in detail in the block diagram
The device requires a rail configuration. Programming this configuration through I2C PMBus commands is not straight-forward, and has no mainline driver support, which is why programming header J8
has been added.
Note that the regulator driving pins are wired to IC25
and IC38
SN74CB3T325 multiplexers, which allows the user to select the sequencing mode with jumper W1
. When the jumper grounds the mux_select
net, the DC/DC and LDO regulators are sequenced by their respective power good
pins. This allows booting the card without the power controller configured. Note however that the power-off sequencing requirements are not respected in this case.
Device configuration
See also the Design block diagram here, page 2, for a synoptic of the power sequence. There has been 8 rails configured for the FASEC, although there's more rails on the card - only the ones with voltage and/or current monitoring are made available. Sequencing all rails is possible through the SEQn_GO hardware signals, which are connected to the remaining regulators enable inputs.
For each rail, dependencies on other rails and GPIs have been configured. 4 GPIs are used as a dependency, they are connected to the power-good outputs of regulators which have no voltage/current surveillance. Somehow counter-intuitive is the way a rail Enable is shown in Fusion GUI - it's actually an controller output that will be asserted when all the mentioned conditions are met. SEQ2_GO
and SEQ5_GO
are not directly controlled by a rail and are as such configured as Logic Controlled GPOs, with dependencies on other rails and GPIs.
Programming
PMBus
Program the UCD90120 power controller using a MS Windows machine and the TI USB-cable connected to J8
; files can be found at the gateware repo's ./misc/ folder. The configuration was done with Fusion Digital Power Designer.
JTAG
The UCD90120 JTAG pins are available on header J9
to provide a possibility to program an image file without requiring a MS Windows machine and the TI USB-PMBus cable. To enable the JTAG mode, a short to ground or an open condition on either address pin will cause an address 126 (0x7E) to be generated which enables JTAG mode [datasheet]. This has not been tested.
DC/DC Converters
- TI LMZ31707, 7A buck with integrated inductor, switching frequency 750 kHz
- TI TLV62150, 1A, and TLV62130, 3A, bucks, switching frequency 2.5 MHz
Linear regulators
- TI TPS74901, 3A LDO
- TI LT1175, 0.5A negative LDO for N5V0
Isolated external I2C bus
J2
is a RJ12 connector which interfaces an I2C bus, coming from the SoC, to connect peripheral devices. IC3
is a ADUM1250 digital isolater which also boosts the signal level to 5V.
Its original purpose was to interface a digital patch panel for the CERN fast-interlock project. For this project two fmc-dio-10i-8o cards are often plugged-in the FMC slots and thus make a total of 20 inputs and 16 outputs available. For diagnosis and debugging it was important to have visible LEDs that reflect the status of these signals and in order to save connector-pins, this external I2C bus was incorporated. It interfaces a custom patch panel but could really interface any I2C slave.
Watchdog surveyed outputs
The card outputs OUT5
and OUT6
are surveyed, which means that both SoC PS & PL needs to output a fixed frequency for this outputs to function normally. In case of a watchdog failure, e.g. PS CPU down or PL bitstream missing, these outputs will assert high at a fixed frequency (T of 900ms) controlled by LTC2917 IC65
and IC74
Voltage supervisor and watchdog timer. This was required by the project to make sure that certain equipment receives cyclic triggers in case of board failure. In addition to the watchdog frequencies, they also monitor the following power nets: P2V5
, P5V0
and P3V3
.