FPGA & ARM SoC FMC Carrier (FASEC)

Project description

This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA 57) with additional 200 kSPS bipolar analog inputs, Ethernet connectivity and fail-safe functionality.
The card has been developed within CERN's TE-ABT group for the Fast Interlocks Detection System (FIDS) project.

The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030 that consists of two silicon ARM cores and FPGA fabric. The idea is to implement fast interlocking logic (<100ns reaction time, 1 ns resolution measurements) in the FPGA while the processor, running Embedded GNU/Linux, runs user applications to control deterministically the equipment and communicate with other devices and CERN's Controls MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources and support the White Rabbit timing and control network. Stand-alone board for use in a 19" rack 1U crate (aka pizza-box).

Design draft documents for review (February 2016)

• Block diagram
• Schematics and Altium project
• Power rail calculations

Main Features

• XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e. Programmable Logic) and Dual ARM® Cortex™-A9 MPCore at 1 GHz (called PS, i.e. Processing System)
• Two Low-Pin Count FMC slots
  • FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
  • FMC2 connectivity: Vadj fixed to 1.8V, 34 differential pairs, JTAG, I2C
• FPGA configuration
  • From QSPI flash, Ethernet (through U-Boot bootloader) or MicroSD card
• Clocking resources
  • 1x 33.33 MHz fixed oscillator, SoC main clock (clock distribution to PL possible)
  • 1x 125 MHz fixed oscillator for the FPGA fabric
  • 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
  • 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
  • 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
• On-board memories
  • 2x 512 MByte (4 Gbit) DDR3L (MT41K256M16HA-125:E)
  • 2x 128 Mbit QSPI flash for FPGA bitstream and Linux kernel & root file system storage (S25FL128SAGMFIR01)
• Miscellaneous
  • UCD90120ARGC power controller (programmable over JTAG) to survey power rails and manage power-on and power-off sequence
  • Xilinx-style JTAG connector
  • 2x hexadecimal switches (for settings selection)
  • UART over a Micro-USB connector (FT232RL)
• Front panel
  • 6x LEMO-00 analog input
  • 1x SFP port (White Rabbit compatible)
  • 2x LEMO/SMC inputs (5V)
  • 2x LEMO/SMC outputs capable of driving 3.3V @ 50 ohm
  • 1x mini displayPort connector for high-speed serial card-to-card GTP link
  • 8x Programmable LED (4 by PL, 4 by PS)
  • POR Reset push button
• Back panel
  • 2x 100 Mbit Ethernet RJ45 ports (1 interface, switched)
  • D-Sub 9 connector for FIDS patch panel
  • D-Sub 9 connector with 2x fail-safe 2xNC channels
• 10-layer PCB

Project information

• Official production documentation: "EDA-xxxxx"
• Specifications
  • Fast Interlocks Detection System for switch and machine protection
• Users
• Software
• Frequently Asked Questions

Releases

Latest:*

• Hardware: v3.0 - EDA-02530-V3-0
• Gateware:
• Embedded Linux distribution: see /project/embedded-linux

All Gateware releases:* See the Releases page.

Contacts

Commercial producers

• none

General question about project

• Pieter van Trappen - CERN

Status

03 Februarty 2016