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Last edited by Vasco Guita

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FPGA & ARM SoC FMC Carrier (FASEC)

Project description

This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA 57) with additional 200 kSPS bipolar analog inputs, Ethernet connectivity and fail-safe functionality.
The card has been developed within CERN's TE-ABT group for the Fast Interlocks Detection System (FIDS) project.

The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030 that consists of two silicon ARM cores and FPGA fabric. The idea is to implement fast interlocking logic (<100ns reaction time, 1 ns resolution measurements) in the FPGA while the processor, running Embedded GNU/Linux, runs user applications to control deterministically the equipment and communicate with other devices and CERN's Controls MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources and support for the White Rabbit timing and control network. Stand-alone board for use in a 19" rack 1U crate (aka pizza-box).


Main Features

  • XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e. Programmable Logic) and Dual ARM Cortex-A9 MPCore at 1 GHz (called PS, i.e. Processing System)
  • Two Low-Pin Count FMC slots
    • FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
    • FMC2 connectivity: Vadj fixed to 1.8V, 34 differential pairs, JTAG, I2C
  • FPGA configuration
    • From QSPI flash, Ethernet (through U-Boot bootloader) or MicroSD card
  • Clocking resources
    • 1x 33.33 MHz fixed oscillator, SoC main clock (clock distribution to PL possible)
    • 1x 125 MHz fixed oscillator for the FPGA fabric
    • 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
    • 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
    • 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
  • On-board memories
    • 2x 512 MByte (4 Gbit) DDR3L (MT41K256M16HA-125:E)
    • 2x 128 Mbit QSPI flash for FPGA bitstream and Linux kernel & root file system storage (S25FL128SAGMFIR01)
  • Miscellaneous
    • UCD90120ARGC power controller (programmable over JTAG) to survey power rails and manage power-on and power-off sequence
    • Xilinx-style JTAG connector
    • 2x hexadecimal switches (for settings selection)
    • UART over a Micro-USB connector (FT232)
  • Front panel
    • 6x LEMO-00 analog input (+-10V range; 200 KSPS)
    • 1x SFP port (White Rabbit compatible)
    • 2x LEMO/SMC inputs (5V)
    • 2x LEMO/SMC outputs capable of driving 3.3V @ 50 ohm
    • 1x USB3.0 A connector for high-speed serial card-to-card GTP link (no USB functionality!)
    • 8x Programmable LED (4 by PL, 4 by PS)
    • POR Reset push button
  • Back panel
    • 2x 100 Mbit Ethernet RJ45 ports (1 interface, switched)
    • RJ11 connector for FIDS patch panel
    • D-Sub 15 connector with isolated 4x fail-safe NC contact channels and 2x 24V input channels
  • 10-layer PCB

Project information

Hardware design notes

See the sub-page Hardware design notes

Pizza-box enclosure/case and cooling fan

A COTS METcase product, M6219145, has been modified for the FASEC with cut-outs and serigraph text for the connectors. The design drawings for the modifications can be found here: metacse_M6219145_fasec_modifs.zip.

Because this design is used in fast pulsed systems with racks that have a low-impedance connection to the pulsed ground in front, a conductive front-panel has been requested from the supplier. This is achieved through a Interlox 338 coating on the aluminium.

The crate is equipped with a Sunon MF35101V2 fan with a female Molex 22-01-2027 connector.

Power supply

As indicated in the schematics, the card's power supply should meet the following specifications:

Voltage power
5V 43W
12V 25W
-12V 2W

The Artesyn LPT102-M is the suggested power supply, that meets the above specification and integrates nicely in the enclosure.

Price indications

All price indications come from the latest x25 pieces V3 production.

Component price indication in CHF
enclosure 130
card production 240
card assembly 200
components 800

Board tests

Prototype-tests
Prototype-White-Rabbit-tests

Miscellaneous

Official production documentation: http://edms.cern.ch/nav/EDA-03288
Specifications

Releases

Design documents after review (March 2016)

Updated/new:

Unchanged:

Design documents for review (February 2016)

Contacts

Commercial producers

  • none

General question about project

Status

Date Event
12-02-2015 Start of specification as part of the FIDS project.
03-02-2016 Schematics ready for review (v0.4), all data uploaded.
10-02-2016 TE-ABT & BE-CO reviews finished
22-02-2016 PCB routing started by designer - focus on critical components
23-03-2016 Schematics & PCB transfer (v0.5) to CERN's Design Office for PCB routing
09-05-2016 PCB design finished, launch of prototype production (2x)
14-07-2016 First prototype available for testing
25-07-2016 Main components validated: Zynq PS & PL, DDR3, power supplies and sequencer
14-08-2017 Full board validated in operation, implement 2nd iteration schematics & PCB
11-09-2017 Pre-series production ordered (10x)
18-12-2017 Pre-series boards (10x) received.
08-02-2019 Series boards (25x) received

09 April 2019