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 ## Project description
 
-A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog
-inputs and fail-safe functionality. It has memory and clocking resources
-and supports the White Rabbit timing and control network. Stand-alone
-board for use in a 'pizza-box'.
+This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA
+57) with additional 200 kSPS bipolar analog inputs, Ethernet
+connectivity and fail-safe functionality. The card has been developed
+within CERN's [TE-ABT
+group](http://te-dep.web.cern.ch/content/accelerator-beam-transfer-group-abt)
+for the Fast Interlocks Detection System (FIDS). It has memory and
+clocking resources and supports the White Rabbit timing and control
+network. Stand-alone board for use in a 'pizza-box'.
 
 *TEMPLATE, PLEASE
 MODIFY**