... | ... | @@ -19,7 +19,21 @@ MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources |
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and support for the White Rabbit timing and control network. Stand-alone
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board for use in a 19" rack 1U crate (aka pizza-box).
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## Design documents for review (February 2016)
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## Final design documents after review (March 2016)
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Updated/new:
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- "Schematics v0.5 and Altium project"
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- [Test project to verify I/O port mapping with synthesis
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(Vivado 2015.4)](https://gitlab.cern.ch/te-abt-ec/FASEC_test)
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Unchanged:
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- [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram)
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- [Power rail calculations](https://www.ohwr.org/project/fasec/wikis/Documents/Design-power-calculations)
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h2. Design documents for review (February 2016)
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<!-- end list -->
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- [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram)
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- [Schematics v0.4 and Altium
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