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@@ -19,7 +19,21 @@ MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources
 and support for the White Rabbit timing and control network. Stand-alone
 board for use in a 19" rack 1U crate (aka pizza-box).
 
-## Design documents for review (February 2016)
+## Final design documents after review (March 2016)
+
+Updated/new:
+
+  - "Schematics v0.5 and Altium project"
+  - [Test project to verify I/O port mapping with synthesis
+    (Vivado 2015.4)](https://gitlab.cern.ch/te-abt-ec/FASEC_test)
+
+Unchanged:
+
+  - [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram)
+  - [Power rail calculations](https://www.ohwr.org/project/fasec/wikis/Documents/Design-power-calculations)  
+    h2. Design documents for review (February 2016)
+
+<!-- end list -->
 
   - [Block diagram](https://www.ohwr.org/project/fasec/wikis/Documents/Design-block-diagram)
   - [Schematics v0.4 and Altium