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@@ -7,9 +7,15 @@ This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA
 connectivity and fail-safe functionality. The card has been developed
 within CERN's [TE-ABT
 group](http://te-dep.web.cern.ch/content/accelerator-beam-transfer-group-abt)
-for the Fast Interlocks Detection System (FIDS). It has memory and
-clocking resources and supports the White Rabbit timing and control
-network. Stand-alone board for use in a 'pizza-box'.
+for the Fast Interlocks Detection System (FIDS) project. The main
+controller is a System-on-a-Chip from Xilinx®, the Zynq XCZ030 that
+consists of two silicon ARM (R) cores and FPGA fabric. The idea is to
+implement fast interlocking logic (\<100ns) in the FPGA while the
+processor, running Embedded GNU/Linux, runs user applications to control
+the equipment and communicate with other devices and CERN's Controls
+MiddelWare (CMW). Additionally there is DDR3L memory, clocking resources
+and support the White Rabbit timing and control network. Stand-alone
+board for use in a 'pizza-box'.
 
 *TEMPLATE, PLEASE
 MODIFY**