Commits · 75b66789a026e62eacc744b14495cc678c6ab28d · Projects / FPGA and ARM SoC FMC Carrier FASEC · GitLab

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Oct 19, 2016
- first functional EDA03287 IP core implemented - IO read/write possible for... · 75b66789
  Pieter Van Trappen authored 8 years ago
```
first functional EDA03287 IP core implemented - IO read/write possible for both FMC slots; software updated accordingly
```
  75b66789
Sep 13, 2016
- modified .gitignore to include .metadata for Eclipse workspace settings · 031c093f
  Pieter Van Trappen authored 8 years ago
  
  031c093f
Aug 31, 2016
- no functional changes but updated IP cores which now properly used the library IP · 3837ec42
  Pieter Van Trappen authored 8 years ago
  
  3837ec42
- No gateware changes, test of the I2C communication successful - EEPROM and I2C mux · 0ff6ad73
  Pieter Van Trappen authored 8 years ago
  
  0ff6ad73
- new fasec_hwtest IP used (modular FMC); I2C code extended; synthesized with 2x EDA-0NONE · 20c89525
  Pieter Van Trappen authored 8 years ago
  
  20c89525
Aug 30, 2016
- 2nd OC I2C master added for FASEC EEPROM; update fasec_hwtest IP; bugfix for OCI2C reads · d6fc45f7
  Pieter Van Trappen authored 8 years ago
  
  d6fc45f7
Aug 26, 2016
- OpenCores I2C master with AXI4-bridge, from cores, added and tested; draft software driver as well · d1e57cd0
  Pieter Van Trappen authored 8 years ago
  
  d1e57cd0
Aug 03, 2016
- hwtest IP added (LEDs only, no AXI4); full DDR3 GB test in SDK · 17e7f87c
  Pieter Van Trappen authored 8 years ago
  
  17e7f87c
Jul 29, 2016
- Ethernt PHY working (length mismatch though), started to implement first hw IP for PL · eafbd6a8
  Pieter Van Trappen authored 8 years ago
  
  eafbd6a8
Jul 27, 2016
- initial commit - temp to work from home · e292096e
  Pieter Van Trappen authored 8 years ago
  
  e292096e