after synthesis, went well with hdl_lib the same version everywhere (bbdc1b6c) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC · GitLab

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FPGA and ARM SoC FMC Carrier FASEC
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bbdc1b6c

Commit bbdc1b6c authored 7 years ago by

Pieter Van Trappen

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after synthesis, went well with hdl_lib the same version everywhere

parent fbf1ca09

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Changes 3

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FASEC_prototype.srcs/sources_1/bd/system_design/ipshared/user.org/fasec_hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd 3 additions, 2 deletions

...hwtest_v3_2_0/FASEC_hwtest.srcs/sources_1/new/top_mod.vhd
FASEC_prototype.xpr 8 additions, 0 deletions

FASEC_prototype.xpr
firmware/system_design_wrapper.bit 0 additions, 0 deletions

firmware/system_design_wrapper.bit

with 11 additions and 2 deletions

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