block-design modified for testing FMC1 external i2c connection (to patch-panel):
* axi_wb_i2c_master_1 removed * mdio_spi now connected to an utility buffer instead of i2c_master * external i2c connection at axi_wb_i2c_master_0 * tcl script modified to run all unfinished OOC runs, however not in parallel * bitstream and hdf generated; tcl build script updated
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- .gitignore 1 addition, 0 deletions.gitignore
- FASEC_prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc 25 additions, 45 deletions..._prototype.srcs/constrs_1/new/fasec_constraints_synth.xdc
- FASEC_prototype.srcs/sources_1/bd/system_design/hdl/system_design_wrapper.vhd 42 additions, 36 deletions.../sources_1/bd/system_design/hdl/system_design_wrapper.vhd
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci 1 addition, 1 deletion...wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml 1 addition, 1 deletion...wb_i2c_master_0_1/system_design_axi_wb_i2c_master_0_1.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci 1 addition, 1 deletion...wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_axi_wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml 1 addition, 1 deletion...wb_i2c_master_2_0/system_design_axi_wb_i2c_master_2_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci 1 addition, 1 deletion...esign_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml 1 addition, 1 deletion...esign_fasec_hwtest_0_0/system_design_fasec_hwtest_0_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_util_ds_buf_0_0/system_design_util_ds_buf_0_0.xci 107 additions, 0 deletions..._design_util_ds_buf_0_0/system_design_util_ds_buf_0_0.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_util_ds_buf_0_0/system_design_util_ds_buf_0_0.xml 1691 additions, 0 deletions..._design_util_ds_buf_0_0/system_design_util_ds_buf_0_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci 5 additions, 5 deletions...system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml 5 additions, 5 deletions...system_design_xadc_wiz_0_0/system_design_xadc_wiz_0_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xci 14 additions, 14 deletions...m_design/ip/system_design_xbar_0/system_design_xbar_0.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xbar_0/system_design_xbar_0.xml 14 additions, 14 deletions...m_design/ip/system_design_xbar_0/system_design_xbar_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_2_0/system_design_xlconstant_2_0.xci 39 additions, 0 deletions...em_design_xlconstant_2_0/system_design_xlconstant_2_0.xci
- FASEC_prototype.srcs/sources_1/bd/system_design/ip/system_design_xlconstant_2_0/system_design_xlconstant_2_0.xml 69 additions, 0 deletions...em_design_xlconstant_2_0/system_design_xlconstant_2_0.xml
- FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bd 74 additions, 42 deletions...rototype.srcs/sources_1/bd/system_design/system_design.bd
- FASEC_prototype.srcs/sources_1/bd/system_design/system_design.bxml 20 additions, 12 deletions...totype.srcs/sources_1/bd/system_design/system_design.bxml
- FASEC_prototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui 122 additions, 117 deletions...ototype.srcs/sources_1/bd/system_design/ui/bd_7f01d80e.ui
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