Updated with submodule FIDSIP that ORs the CMPin and extenedcmpin in hardware.... (0de19280) · Commits · Projects / FPGA and ARM SoC FMC Carrier FASEC

Commit 0de19280 authored 7 years ago by

Eino J. Oltedal

Updated with submodule FIDSIP that ORs the CMPin and extenedcmpin in hardware....

Updated with submodule FIDSIP that ORs the CMPin and extenedcmpin in hardware. This avoids problems with signals that are longer than the extended signal

parent c2c22ba9

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FASEC_prototype.ip_user_files/bd/system_design/hdl/system_design.vhd 2688 additions, 1267 deletions

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FASEC_prototype.ip_user_files/bd/system_design/ipshared/cern.ch/axi_wb_i2c_master_v3_2_0/ip_cores/hdl_lib/modules/general/doubleBufferVector.vhd 0 additions, 70 deletions

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