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Euro ADC 65M 14b 40cha hw PUMA-hw
Commit c09d1274 authored by David Cussans's avatar David Cussans
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Checking in CPLD code for pc051b

parent 38654766
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Showing with 535 additions and 18 deletions
firmware/CPLD/Mutiplexer.gise
View file @ c09d1274
......@@ -80,7 +80,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1487349464" xil_pn:in_ck="-48188926558580606" xil_pn:name="TRANEXT_xstsynthesize_xbr" xil_pn:prop_ck="-2857206319670813617" xil_pn:start_ts="1487349452">
<transform xil_pn:end_ts="1491837205" xil_pn:in_ck="-48188926558580606" xil_pn:name="TRANEXT_xstsynthesize_xbr" xil_pn:prop_ck="-2857206319670813617" xil_pn:start_ts="1491837192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -100,8 +100,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1487349470" xil_pn:in_ck="-9071228455691267137" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="-7850409713972882024" xil_pn:start_ts="1487349464">
<transform xil_pn:end_ts="1491837211" xil_pn:in_ck="-9071228455691267137" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="-7850409713972882024" xil_pn:start_ts="1491837205">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Multiplexer.bld"/>
<outfile xil_pn:name="Multiplexer.ngd"/>
......@@ -109,7 +110,7 @@
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
<transform xil_pn:end_ts="1487349482" xil_pn:in_ck="-2172652535546727998" xil_pn:name="TRANEXT_vm6File_xbr" xil_pn:prop_ck="-6011982587378100439" xil_pn:start_ts="1487349470">
<transform xil_pn:end_ts="1491837223" xil_pn:in_ck="-2172652535546727998" xil_pn:name="TRANEXT_vm6File_xbr" xil_pn:prop_ck="-6011982587378100439" xil_pn:start_ts="1491837211">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -130,7 +131,7 @@
<outfile xil_pn:name="Multiplexer_html"/>
<outfile xil_pn:name="Multiplexer_pad.csv"/>
</transform>
<transform xil_pn:end_ts="1487349483" xil_pn:in_ck="-2172652535546719134" xil_pn:name="TRANEXT_crtProg_xbr" xil_pn:prop_ck="5245363024343" xil_pn:start_ts="1487349482">
<transform xil_pn:end_ts="1491837225" xil_pn:in_ck="-2172652535546719134" xil_pn:name="TRANEXT_crtProg_xbr" xil_pn:prop_ck="5245363024343" xil_pn:start_ts="1491837223">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Multiplexer.jed"/>
......@@ -139,7 +140,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
</transform>
......@@ -147,7 +150,9 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/>
<outfile xil_pn:name="_impact.log"/>
</transform>
......
firmware/CPLD/src/Multiplexer.vhd
View file @ c09d1274
......@@ -68,7 +68,7 @@ entity Multiplexer is
power_switch_high_off : in std_logic; -- goes high when switch in "off" position
fpga_en1 : out std_logic; -- JTAG enable signal to TE0712
fpga_resin : out std_logic; -- reset signal to TE0712
gpio : out std_logic_vector(9 downto 0)
gpio : inout std_logic_vector(9 downto 0)
);
end Multiplexer;
......@@ -93,12 +93,14 @@ begin
-- bodge
--gpio <= ( others => '0');
gpio(4 downto 0) <= bus_select;
--gpio(4 downto 0) <= bus_select;
--gpio(9 downto 5) <= ( others => '0');
gpio(5) <= SDA_out_from_FPGA ;
gpio(6) <= s_SDA_in_to_FPGA ;
gpio(7) <= SCL_from_FPGA ;
-- C26 on J16 - GPIO(5) , J8 - GPIO(7) need to be inputs ( will pull ups )
gpio(3 downto 0) <= ( others => '1'); -- turn on amplifier boards.
--gpio(4) <= '0';
--gpio(5) <= SDA_out_from_FPGA ;
--gpio(6) <= s_SDA_in_to_FPGA ;
--gpio(7) <= SCL_from_FPGA ;
SDA_in_to_FPGA <= s_SDA_in_to_FPGA ;
......@@ -131,7 +133,8 @@ begin
-- Bodge
--temp_Alarm_Led_o <= power_switch_high_on;
--s_powerSwitch ;
temp_Alarm_Led_o <= bus_select(1);
--temp_Alarm_Led_o <= bus_select(1);
temp_Alarm_Led_o <= '1'; -- turn on the LED..
-- Bodge - prevent optimization
process (clk_in)
......
firmware/CPLD/src/i2c_deglitch_fsm.vhd 0 → 120000
View file @ c09d1274
../hdl_designer/pc051b_cpld_lib/hdl/i2c_deglitch_fsm.vhd
\ No newline at end of file
firmware/CPLD/src/pc051b_cpld.ucf 0 → 100644
View file @ c09d1274
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "BUS_SELECT<0>" LOC = "C1" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<1>" LOC = "B1" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<2>" LOC = "A2" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<3>" LOC = "A3" | IOSTANDARD = LVCMOS33 ;
NET "BUS_SELECT<4>" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
NET "CSA_to_ADC<0>" LOC = "L1" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<1>" LOC = "R1" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<2>" LOC = "R4" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<3>" LOC = "T7" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<4>" LOC = "R12" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<5>" LOC = "R16" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<6>" LOC = "M15" | IOSTANDARD = LVCMOS18 ;
NET "CSA_to_ADC<7>" LOC = "K14" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<0>" LOC = "L2" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<1>" LOC = "T1" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<2>" LOC = "R5" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<3>" LOC = "T8" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<4>" LOC = "R13" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<5>" LOC = "P16" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<6>" LOC = "L15" | IOSTANDARD = LVCMOS18 ;
NET "CSB_to_ADC<7>" LOC = "J14" | IOSTANDARD = LVCMOS18 ;
NET "SCK_from_FPGA" LOC = "A6" | IOSTANDARD = LVCMOS33 ;
NET "SCK_to_ADC<0>" LOC = "J1" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<1>" LOC = "M1" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<2>" LOC = "R2" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<3>" LOC = "T5" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<4>" LOC = "R8" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<5>" LOC = "R14" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<6>" LOC = "P15" | IOSTANDARD = LVCMOS18 ;
NET "SCK_to_ADC<7>" LOC = "L16" | IOSTANDARD = LVCMOS18 ;
NET "SCL_from_FPGA" LOC = "A9" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<0>" LOC = "A11" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<1>" LOC = "A13" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<2>" LOC = "A15" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<3>" LOC = "B16" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<4>" LOC = "E16" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<5>" LOC = "G16" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<6>" LOC = "B11" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<7>" LOC = "B13" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<8>" LOC = "B15" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<9>" LOC = "E15" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<10>" LOC = "G15" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<11>" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
NET "SCL_to_I2C<9>" LOC = "J3" | IOSTANDARD = LVCMOS18 ;
#NET "SCL_to_I2C<12>" LOC = "B7" | IOSTANDARD = LVCMOS33 ;
#NET "SCL_to_I2C<13>" LOC = "J3" | IOSTANDARD = LVCMOS18 ;
NET "SDA_I2C<0>" LOC = "A12" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<1>" LOC = "A14" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<2>" LOC = "A16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<3>" LOC = "C16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<4>" LOC = "F16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<5>" LOC = "H16" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<6>" LOC = "B12" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<7>" LOC = "B14" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<8>" LOC = "D15" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<9>" LOC = "F15" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<10>" LOC = "H15" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<11>" LOC = "B10" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "SDA_I2C<9>" LOC = "K3" | IOSTANDARD = LVCMOS18 | PULLUP ;
#NET "SDA_I2C<12>" LOC = "B8" | IOSTANDARD = LVCMOS33 | PULLUP ;
#NET "SDA_I2C<13>" LOC = "K3" | IOSTANDARD = LVCMOS18 | PULLUP ;
NET "SDA_in_to_FPGA" LOC = "A8" | IOSTANDARD = LVCMOS33 ;
NET "SDA_out_from_FPGA" LOC = "A7" | IOSTANDARD = LVCMOS33 ;
NET "SDI_to_ADC<0>" LOC = "J2" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<1>" LOC = "N1" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<2>" LOC = "R3" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<3>" LOC = "T6" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<4>" LOC = "R9" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<5>" LOC = "R15" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<6>" LOC = "N15" | IOSTANDARD = LVCMOS18 ;
NET "SDI_to_ADC<7>" LOC = "K16" | IOSTANDARD = LVCMOS18 ;
#
#NET "SDI_to_FPGA" LOC = "A4" | IOSTANDARD = LVCMOS33 ;
# This line should come *from* FPGA.
NET "SDI_to_FPGA" LOC = "A5" | IOSTANDARD = LVCMOS33 ;
#
# And this line should go to the FPGA.
#NET "SDO_from_FPGA" LOC = "A5" | IOSTANDARD = LVCMOS33 ;
NET "SDO_from_FPGA" LOC = "A4" | IOSTANDARD = LVCMOS33 ;
NET "SDOA_from_ADC<0>" LOC = "K1" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<1>" LOC = "N2" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<2>" LOC = "T3" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<3>" LOC = "R6" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<4>" LOC = "T10" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<5>" LOC = "T15" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<6>" LOC = "N16" | IOSTANDARD = LVCMOS18 ;
NET "SDOA_from_ADC<7>" LOC = "K15" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<0>" LOC = "K2" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<1>" LOC = "P1" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<2>" LOC = "T4" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<3>" LOC = "R7" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<4>" LOC = "R10" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<5>" LOC = "T16" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<6>" LOC = "M16" | IOSTANDARD = LVCMOS18 ;
NET "SDOB_from_ADC<7>" LOC = "J15" | IOSTANDARD = LVCMOS18 ;
NET "SPI_CSN_FROM_FPGA" LOC = "H1" | IOSTANDARD = LVCMOS33 ;
NET "SFP_present<0>" LOC = "D2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_los<0>" LOC = "E2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_tx_fault<0>" LOC = "F2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_present<1>" LOC = "G3" |IOSTANDARD = LVCMOS33 ;
NET "SFP_los<1>" LOC = "H2" |IOSTANDARD = LVCMOS33 ;
NET "SFP_tx_fault<1>" LOC = "H3" |IOSTANDARD = LVCMOS33 ;
NET "CLK_IN" LOC = "P5" ;
NET "temp_Alarm_i" LOC = "B2" | IOSTANDARD = LVCMOS33 ;
NET "temp_Alarm_Led_o" LOC = "C4" |IOSTANDARD = LVCMOS33 ;
NET "POR_i" LOC = "D3" | IOSTANDARD = LVCMOS33 ;
NET "PGood_from_FPGA_i" LOC = "B6" |IOSTANDARD = LVCMOS33 ;
NET "PGood_from_HDMI_i" LOC = "C7" |IOSTANDARD = LVCMOS33 ;
NET "FPGA_Power_Enable_o" LOC = "B3" |IOSTANDARD = LVCMOS33 ;
NET "PGood_o" LOC = "F3" |IOSTANDARD = LVCMOS33 ;
NET "PGood3v3_o" LOC = "B7" | IOSTANDARD = LVCMOS33 ;
NET "power_switch_low_on" LOC = "C3" |IOSTANDARD = LVCMOS33 | PULLUP;
NET "power_switch_low_off" LOC = "E3" |IOSTANDARD = LVCMOS33 | PULLUP ;
NET "fpga_en1" LOC = "B4" |IOSTANDARD = LVCMOS33 ;
NET "fpga_resin" LOC = "B5" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<0>" LOC = "E14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<1>" LOC = "F14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<2>" LOC = "G14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<3>" LOC = "H14" |IOSTANDARD = LVCMOS33 ;
NET "GPIO<4>" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<5>" LOC = "F15" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<6>" LOC = "H15" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<7>" LOC = "B10" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<8>" LOC = "E15" | IOSTANDARD = LVCMOS33 ;
NET "GPIO<9>" LOC = "G15" | IOSTANDARD = LVCMOS33 ;
#NET "GPIO<10>" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
firmware/CPLD/src/pc051b_cpld.vhd 0 → 100644
View file @ c09d1274
-- Takes single SPI bus from FPGA and multiplexes onto multiple SPI busses
-- Takes single I2C bus from FPGA and multiplexes onto multiple SPI busses
-- ( splits I2C data line into SDA_from_fpga and SDA_to_fpga. )
--
-- Written by Jules Desjardin, June 2016
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Multiplexer is
generic (
g_NUM_SPI : natural := 8; -- Number of SPI devices
g_NUM_I2C : natural := 10;
g_NUM_SFP : natural := 2); -- number of I2C busses
port (
-- SPI busses to ADC chips
-- There are 8 ADC chips. Each chip behaves like two SPI devices
SCK_to_ADC : out std_logic_vector(g_NUM_SPI-1 downto 0);
SDI_to_ADC : out std_logic_vector(g_NUM_SPI-1 downto 0);
SDOA_from_ADC : in std_logic_vector(g_NUM_SPI-1 downto 0);
SDOB_from_ADC : in std_logic_vector(g_NUM_SPI-1 downto 0);
CSA_to_ADC : out std_logic_vector(g_NUM_SPI-1 downto 0);
CSB_to_ADC : out std_logic_vector(g_NUM_SPI-1 downto 0);
-- I2C busses to analogue boards etc.
-- There are 14 I2C busses
-- Eight to 96-way DIN connectors ( 2 x 4 ) 3.3V
-- Two SFP cages , 3.3V
-- Two I2C to frame for temperature monitors , 3.3V
-- Si50345 clock chip , 1.8V
-- Unique ID chip + current/voltage monitors , 3.3V
SDA_I2C : inout std_logic_vector(g_NUM_I2C-1 downto 0);
SCL_to_I2C : out std_logic_vector(g_NUM_I2C-1 downto 0);
-- Bus select line from FPGA
bus_select : in std_logic_vector(4 downto 0);
-- SPI signals to FPGA
SPI_CSN_FROM_FPGA : in std_logic;
SDI_to_FPGA : out std_logic;
SDO_from_FPGA : in std_logic;
SCK_from_FPGA : in std_logic;
-- I2C signal to FPGA
SDA_out_from_FPGA : in std_logic;
SDA_in_to_FPGA : out std_logic;
SCL_from_FPGA : in std_logic;
-- Signals to SFP cages
--- Bodge for now - set to output to stop optimization
SFP_present : in std_logic_vector(g_NUM_SFP-1 downto 0);
SFP_LOS : out std_logic_vector(g_NUM_SFP-1 downto 0);
SFP_tx_fault: out std_logic_vector(g_NUM_SFP-1 downto 0);
clk_in : in std_logic; -- Needed for SPI slave in CPLD and power on-off / thermal shutdown
temp_Alarm_i : in std_logic ; -- Driven high by temp monitor if board overheats
temp_Alarm_Led_o : out std_logic ; -- goes high if CPLD shuts down due to over temperature
POR_i : in std_logic ; -- driven low by power-on-reset chip when power cycled. Causes PGood_o and FPGA_Power_Enable_o to drop low
PGood_from_FPGA_i : in std_logic; -- goes high when power rails are up and stable on FPGA
PGood_from_HDMI_i : in std_logic; -- goes high when power enabled by off-board control
FPGA_Power_Enable_o : out std_logic; -- goes high to enable DC-DC converters on Trenz FPGA board.
PGood3v3_o : out std_logic; -- goes high to enable the +3.3V supply for FPGA and clock circuit
PGood_o : out std_logic; -- goes high enable the +2.5V and +1.8V power supplies.
power_switch_low_on : in std_logic ; -- goes high when SPDT toggle switch in "on" position
power_switch_low_off : in std_logic; -- goes high when switch in "off" position
fpga_en1 : out std_logic; -- JTAG enable signal to TE0712
fpga_resin : out std_logic; -- reset signal to TE0712
gpio : inout std_logic_vector(9 downto 0)
);
end Multiplexer;
architecture Multiplexer_arch of Multiplexer is
-- signals
signal bus_select_int : integer range 0 to 21;
signal SPI_number : integer range 0 to g_NUM_SPI-1;
signal s_powerSwitch , s_enabled , s_fpgaPowerEnable , s_TempOK : std_logic := '0';
signal s_SDA_in_to_FPGA : std_logic ;
-- components
begin
-- insts
-- bodge
--gpio <= ( others => '0');
--gpio(4 downto 0) <= bus_select;
--gpio(9 downto 5) <= ( others => '0');
gpio(3 downto 0) <= ( others => '1'); -- turn on amplifier boards.
--gpio(4) <= '0';
--gpio(5) <= SDA_out_from_FPGA ;
--gpio(6) <= s_SDA_in_to_FPGA ;
--gpio(7) <= SCL_from_FPGA ;
SDA_in_to_FPGA <= s_SDA_in_to_FPGA ;
s_enabled <= '1' when
(
PGood_from_HDMI_i = '1' and
s_powerSwitch = '1')
else '0';
-- if power is enabled by front panel switch and HDMI and we haven't overheated.
s_fpgaPowerEnable <= '1' when s_enabled = '1' and s_TempOK = '1' else '0';
-- permanently enable power....
--FPGA_Power_Enable_o <= s_fpgaPowerEnable; -- raise the power enable pin on FPGA
--PGood3v3_o <= s_fpgaPowerEnable; -- turn on the 3.3V power for FPGA and clock. Might want delay.
FPGA_Power_Enable_o <= '1';
PGood3v3_o <= '1';
-- Once FPGA has turned on its DC-DC converters, turn on regulators on board.
-- PGood_o <= '1' when PGood_from_FPGA_i = '1' and s_enabled = '1' and s_TempOK = '1' else '0';
PGood_o <= '1';
-- Set JTAGEN ( fpga_en1) low for normal operation. Only need to set high to program the Lattice Mach02 CPLD on Trenz TE0712
fpga_en1 <='0';
-- set RESIN high for normal operations. (Pulling low will reconfigure the FPGA )
fpga_resin <='1';
-- temp_Alarm_Led_o <='1' when s_TempOK = '0' else '0' ;
-- Bodge
--temp_Alarm_Led_o <= power_switch_low_on;
--s_powerSwitch ;
--temp_Alarm_Led_o <= bus_select(1);
--temp_Alarm_Led_o <= '1'; -- turn on the LED..
--temp_Alarm_Led_o <= power_switch_low_on;
temp_Alarm_Led_o <= s_powerSwitch;
--temp_Alarm_Led_o <= POR_i;
-- Bodge - prevent optimization
process (clk_in)
begin
if rising_edge(clk_in) then
SFP_LOS <= SFP_present;
SFP_tx_fault<= SFP_present;
end if;
end process;
-- Handle on/off switch
process (clk_in)
begin
if rising_edge(clk_in) then
if POR_i = '0' then
s_powerSwitch <= '0';
elsif power_switch_low_on = '0' then
s_powerSwitch <= '1';
elsif power_switch_low_off = '0' then
s_powerSwitch <= '0';
end if;
end if;
end process;
-- Handle over temperature
process (clk_in)
begin
if rising_edge(clk_in) then
if POR_i = '1' then
s_TempOK <= '1';
elsif temp_Alarm_i = '1' then
s_TempOK <= '0';
elsif temp_Alarm_i = '0' and s_enabled = '0' then -- Only reset when power cycled.
s_TempOK <= '1';
end if;
end if;
end process;
-- logic
bus_select_int <= to_integer(unsigned(bus_select));
SPI_number <= to_integer(unsigned(bus_select(3 downto 1)));
-- process
process(bus_select,SDOA_from_ADC,SDOB_from_ADC,SDA_I2C,SDO_from_FPGA,SCK_from_FPGA,SDA_out_from_FPGA,SCL_from_FPGA,bus_select_int,SPI_number,SPI_CSN_FROM_FPGA)
begin
-- Initialization
SDI_to_FPGA <= '0';
SCK_to_ADC <= (others => '0');
SDI_to_ADC <= (others => '0');
CSA_to_ADC <= (others => '1');
CSB_to_ADC <= (others => '1');
SCL_to_I2C <= (others => 'Z');
s_SDA_in_to_FPGA <= '1';
SDA_I2C <= (others => 'Z');
-- SPI
if(SPI_CSN_FROM_FPGA = '0') then
SDI_to_ADC(SPI_number) <= SDO_from_FPGA;
SCK_to_ADC(SPI_number) <= SCK_from_FPGA;
if (bus_select(0) = '0') then
SDI_to_FPGA <= SDOA_from_ADC(SPI_number);
CSA_to_ADC(SPI_number) <= '0';
else
SDI_to_FPGA <= SDOB_from_ADC(SPI_number);
CSB_to_ADC(SPI_number) <= '0';
end if;
end if;
-- I2C
if(bus_select_int < (g_NUM_I2C+1)) then -- only 9 I2C
if (SDA_out_from_FPGA = '0') then
SDA_I2C(bus_select_int) <= '0';
else
SDA_I2C(bus_select_int) <= 'Z';
end if;
s_SDA_in_to_FPGA <= TO_X01(SDA_I2C(bus_select_int));
SCL_to_I2C(bus_select_int) <= SCL_from_FPGA;
end if;
end process;
end Multiplexer_arch;
firmware/CPLD/src/tb_i2c_deglitch.vhd 0 → 100644
View file @ c09d1274
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:36:55 03/10/2017
-- Design Name:
-- Module Name: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/tb_i2c_deglitch.vhd
-- Project Name: pc051c_cpld
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: i2c_deglitch
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_i2c_deglitch IS
END tb_i2c_deglitch;
ARCHITECTURE behavior OF tb_i2c_deglitch IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT i2c_deglitch
PORT(
clk : IN std_logic;
din : IN std_logic;
rst : IN std_logic;
dout : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal din : std_logic := '0';
signal rst : std_logic := '0';
--Outputs
signal dout : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: i2c_deglitch PORT MAP (
clk => clk,
din => din,
rst => rst,
dout => dout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
din <='0';
rst<='1';
-- hold reset state for 100 ns.
wait for 100 ns;
rst<='0';
wait for clk_period*10;
report "Waiting for falling edge clk before setting din high";
-- insert stimulus here
wait until falling_edge(clk);
report "setting Din high";
-- transition high
din <= '1';
-- transition low
wait for clk_period*10;
wait until falling_edge(clk);
din <= '0';
-- transition high
wait for clk_period*10;
wait until falling_edge(clk);
din <= '1';
-- glitch low
wait for clk_period*10;
wait until falling_edge(clk);
din <= '0';
wait until falling_edge(clk);
din <= '1';
-- Glitch high
wait for clk_period*10;
wait until falling_edge(clk);
din <= '0';
wait for clk_period*10;
wait until falling_edge(clk);
din <= '1';
wait until falling_edge(clk);
din <= '0';
wait;
end process;
END;
firmware/pc051c_cpld/Multiplexer_summary.html
View file @ c09d1274
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Multiplexer Project Status (03/24/2017 - 14:50:02)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>Multiplexer Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>pc051c_cpld.xise</TD>
......@@ -13,7 +13,7 @@
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>Multiplexer</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Translated (Failed)</TD>
<TD>Translated</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
......@@ -79,5 +79,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 03/24/2017 - 14:50:02</center>
<br><center><b>Date Generated:</b> 04/10/2017 - 15:34:35</center>
</BODY></HTML>
\ No newline at end of file
firmware/pc051c_cpld/iseconfig/Multiplexer.xreport
View file @ c09d1274
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2017-03-24T14:47:57</DateModified>
<DateModified>2017-04-10T15:34:35</DateModified>
<ModuleName>Multiplexer</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/iseconfig/Multiplexer.xreport</SavedFilePath>
......
firmware/pc051c_cpld/iseconfig/pc051c_cpld.projectmgr
View file @ c09d1274
......@@ -13,7 +13,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000003a9000000020000000000000000000000000200000064ffffffff000000810000000300000002000003a90000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000357000000020000000000000000000000000200000064ffffffff000000810000000300000002000003570000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>Multiplexer - Multiplexer_arch (/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd)</CurrentItem>
</ItemView>
......@@ -31,7 +31,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000003d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000003d80000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000312000000010000000100000000000000000000000064ffffffff000000810000000000000001000003120000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Programming File</CurrentItem>
</ItemView>
......@@ -54,7 +54,7 @@
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000123000000010001000100000000000000000000000064ffffffff000000810000000000000001000001230000000100000000</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000112000000010001000100000000000000000000000064ffffffff000000810000000000000001000001120000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
......
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