Skip to content

E
Euro ADC 65M 14b 40cha hw PUMA-hw
Commit 38654766 authored by David Cussans's avatar David Cussans
Browse files
Options

Checking in files for pc051c - firmware for new board

parent da126428
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 36780 additions and 0 deletions
firmware/pc051c_cpld/Multiplexer.bld 0 → 100644
View file @ 38654766
Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line:
/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-intstyle ise -dd _ngo -uc
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src
/pc051c_cpld.ucf -p xc2c256-FT256-6 Multiplexer.ngc Multiplexer.ngd
Reading NGO file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_
cpld/Multiplexer.ngc" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/sr
c/pc051c_cpld.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <NET "cpld_led<1>" LOC = "H2" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(103)]: NET "cpld_led<1>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "cpld_led<1>" LOC = "H2" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(103)]' could not be found and so the Locate constraint
will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(103)]: NET "cpld_led<1>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "cpld_led<0>" LOC = "E2" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(104)]: NET "cpld_led<0>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "cpld_led<0>" LOC = "E2" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(104)]' could not be found and so the Locate constraint
will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(104)]: NET "cpld_led<0>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "cpld_led<2>" LOC = "E1" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(105)]: NET "cpld_led<2>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "cpld_led<2>" LOC = "E1" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(105)]' could not be found and so the Locate constraint
will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(105)]: NET "cpld_led<2>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "cpld_led<3>" LOC = "F1" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(106)]: NET "cpld_led<3>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<NET "cpld_led<3>" LOC = "F1" |>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(106)]' could not be found and so the Locate constraint
will be removed.
ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD = LVCMOS33 ;>
[/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD
/src/pc051c_cpld.ucf(106)]: NET "cpld_led<3>" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 8
Number of warnings: 4
Total memory usage is 494960 kilobytes
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
One or more errors were found during NGDBUILD. No NGD file will be written.
Writing NGDBUILD log file "Multiplexer.bld"...
firmware/pc051c_cpld/Multiplexer.cmd_log 0 → 100644
View file @ 38654766
xst -intstyle ise -ifn "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer.xst" -ofn "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer.syr"
ngdbuild -intstyle ise -dd _ngo -uc /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf -p xc2c256-FT256-6 Multiplexer.ngc Multiplexer.ngd
firmware/pc051c_cpld/Multiplexer.ngc 0 → 100644
View file @ 38654766
This diff is collapsed.
firmware/pc051c_cpld/Multiplexer.ngr 0 → 100644
View file @ 38654766
This diff is collapsed.
firmware/pc051c_cpld/Multiplexer.prj 0 → 100644
View file @ 38654766
vhdl work "../CPLD/src/pc051c_cpld.vhd"
firmware/pc051c_cpld/Multiplexer.syr 0 → 100644
View file @ 38654766
Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.09 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.09 secs
-->
Reading design: Multiplexer.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "Multiplexer.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "Multiplexer"
Output Format : NGC
Target Device : CoolRunner2 CPLDs
---- Source Options
Top Module Name : Multiplexer
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
Mux Extraction : Yes
Resource Sharing : YES
---- Target Options
Add IO Buffers : YES
MACRO Preserve : YES
XOR Preserve : YES
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : Yes
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Verilog 2001 : YES
---- Other Options
Clock Enable : YES
wysiwyg : NO
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd" in Library work.
Entity <Multiplexer> compiled.
Entity <Multiplexer> (Architecture <Multiplexer_arch>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <Multiplexer> in library <work> (architecture <Multiplexer_arch>) with generics.
g_NUM_I2C = 10
g_NUM_SFP = 2
g_NUM_SPI = 8
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing generic Entity <Multiplexer> in library <work> (Architecture <Multiplexer_arch>).
g_NUM_I2C = 10
g_NUM_SFP = 2
g_NUM_SPI = 8
WARNING:Xst:790 - "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd" line 217: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd" line 219: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd" line 222: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd" line 223: Index value(s) does not match array range, simulation mismatch.
Entity <Multiplexer> analyzed. Unit <Multiplexer> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <Multiplexer>.
Related source file is "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd".
WARNING:Xst:1306 - Output <gpio<9:8>> is never assigned.
WARNING:Xst:647 - Input <PGood_from_FPGA_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <s_fpgaPowerEnable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Register <SFP_tx_fault> equivalent to <SFP_LOS> has been removed
Found 10-bit tristate buffer for signal <SDA_I2C>.
Found 10-bit tristate buffer for signal <SCL_to_I2C>.
Found 2-bit register for signal <SFP_LOS>.
Found 5-bit comparator less for signal <s_SDA_in_to_FPGA$cmp_lt0000> created at line 215.
Summary:
inferred 1 Comparator(s).
inferred 20 Tristate(s).
Unit <Multiplexer> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Registers : 1
2-bit register : 1
# Comparators : 1
5-bit comparator less : 1
# Tristates : 20
1-bit tristate buffer : 20
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <Multiplexer> ...
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : Multiplexer.ngr
Top Level Output File Name : Multiplexer
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : Yes
Target Technology : CoolRunner2 CPLDs
Macro Preserve : YES
XOR Preserve : YES
Clock Enable : YES
wysiwyg : NO
Design Statistics
# IOs : 109
Cell Usage :
# BELS : 296
# AND2 : 103
# AND3 : 13
# AND5 : 5
# GND : 1
# INV : 123
# OR2 : 41
# OR3 : 9
# VCC : 1
# FlipFlops/Latches : 2
# FD : 2
# IO Buffers : 101
# IBUF : 29
# IOBUFE : 10
# OBUF : 52
# OBUFE : 10
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 3.29 secs
-->
Total memory usage is 620776 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 7 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
firmware/pc051c_cpld/Multiplexer.xst 0 → 100644
View file @ 38654766
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn Multiplexer.prj
-ifmt mixed
-ofn Multiplexer
-ofmt NGC
-p xbr
-top Multiplexer
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy Yes
-netlist_hierarchy As_Optimized
-rtlview Yes
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-mux_extract Yes
-resource_sharing YES
-iobuf YES
-pld_mp YES
-pld_xp YES
-pld_ce YES
-wysiwyg NO
-equivalent_register_removal YES
firmware/pc051c_cpld/Multiplexer_envsettings.html 0 → 100644
View file @ 38654766
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='3'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
</tr>
<tr>
<td>LD_LIBRARY_PATH</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//lib/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/lib/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/lib:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/lib/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/lib/lin64</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//lib/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/lib/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/lib:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/lib/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/lib/lin64</td>
</tr>
<tr>
<td>LMC_HOME</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
</tr>
<tr>
<td>PATH</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//bin/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/bin/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/util:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/../../../DocNav:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/bin/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/bin/lin64:<br>/home/phdgc/gopath:<br>/home/phdgc/gopath/bin:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/local/sbin:<br>/usr/bin:<br>/usr/sbin:<br>/usr/libexec/sdcc:<br>/home/phdgc/.local/bin:<br>/home/phdgc/bin:<br>/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim//bin:<br>/software/CAD/Mentor/2014_2015/HDS_2013.1b/bin:<br>/software/CAD/Altera/13.1/quartus/bin:<br>/software/CAD/Altera/13.1/qprogrammer/bin/:<br>/projects/HEP_Instrumentation/cad/tools</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//bin/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/bin/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/util:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/../../../DocNav:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/bin/lin64:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/bin/lin64:<br>/home/phdgc/gopath:<br>/home/phdgc/gopath/bin:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/local/sbin:<br>/usr/bin:<br>/usr/sbin:<br>/usr/libexec/sdcc:<br>/home/phdgc/.local/bin:<br>/home/phdgc/bin:<br>/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim//bin:<br>/software/CAD/Mentor/2014_2015/HDS_2013.1b/bin:<br>/software/CAD/Altera/13.1/quartus/bin:<br>/software/CAD/Altera/13.1/qprogrammer/bin/:<br>/projects/HEP_Instrumentation/cad/tools</td>
</tr>
<tr>
<td>XILINX</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>5280@asimov.phy.bris.ac.uk</td>
<td>5280@asimov.phy.bris.ac.uk</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE</td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead</td>
<td>/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>Multiplexer.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ifmt</td>
<td>&nbsp;</td>
<td>mixed</td>
<td>MIXED</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>Multiplexer</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xbr</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>Multiplexer</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>SPEED</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>as_optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>NO</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-verilog2001</td>
<td>Verilog 2001</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc2c256-FT256-6</td>
<td>None</td>
</tr>
<tr>
<td>-uc</td>
<td>&nbsp;</td>
<td>/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='3'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM) i7-2600S CPU @ 2.80GHz/2018.481 MHz</td>
<td>Intel(R) Core(TM) i7-2600S CPU @ 2.80GHz/1989.599 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>voltar.phy.bris.ac.uk</td>
<td>voltar.phy.bris.ac.uk</td>
</tr>
<tr>
<td>OS Name</td>
<td>Fedora</td>
<td>Fedora</td>
</tr>
<tr>
<td>OS Release</td>
<td>Fedora release 24 (Twenty Four)</td>
<td>Fedora release 24 (Twenty Four)</td>
</tr>
</TABLE>
</BODY> </HTML>
\ No newline at end of file
firmware/pc051c_cpld/Multiplexer_ngdbuild.xrpt 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Fri Mar 24 14:50:01 2017">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//lib/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/lib/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/lib:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/lib/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/lib/lin64"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="5280@asimov.phy.bris.ac.uk"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//bin/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/bin/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/util:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/../../../DocNav:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/bin/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/bin/lin64:/home/phdgc/gopath:/home/phdgc/gopath/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/usr/libexec/sdcc:/home/phdgc/.local/bin:/home/phdgc/bin:/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim//bin:/software/CAD/Mentor/2014_2015/HDS_2013.1b/bin:/software/CAD/Altera/13.1/quartus/bin:/software/CAD/Altera/13.1/qprogrammer/bin/:/projects/HEP_Instrumentation/cad/tools"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="LMC_HOME"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead"/>
</row>
<row stringID="row" value="7">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Fedora"/>
<item stringID="User_EnvOsrelease" value="Fedora release 24 (Twenty Four)"/>
</item>
<item stringID="User_EnvHost" value="voltar.phy.bris.ac.uk"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-2600S CPU @ 2.80GHz"/>
<item stringID="speed" value="1989.599 MHz"/>
</row>
</table>
</section>
<task stringID="NGDBUILD_OPTION_SUMMARY">
<section stringID="NGDBUILD_OPTION_SUMMARY">
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc2c256-FT256-6"/>
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf"/>
</section>
</task>
<task stringID="NGDBUILD_REPORT">
<section stringID="NGDBUILD_DESIGN_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="8"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="4"/>
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="103"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="29"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="52"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="41"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
</section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_AND2" value="103"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND3" value="13"/>
<item dataType="int" stringID="NGDBUILD_NUM_AND5" value="5"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="45"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="123"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="54"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR2" value="41"/>
<item dataType="int" stringID="NGDBUILD_NUM_OR3" value="9"/>
<item dataType="int" stringID="NGDBUILD_NUM_PULLUP" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
</section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/>
</section>
</task>
</application>
</document>
firmware/pc051c_cpld/Multiplexer_summary.html 0 → 100644
View file @ 38654766
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Multiplexer Project Status (03/24/2017 - 14:50:02)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>pc051c_cpld.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>Multiplexer</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Translated (Failed)</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc2c256-6FT256</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>
<font color="red"; face="Arial"><b>X </b></font>
<A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/_xmsgs/*.xmsgs?&DataKey=Error'>8 Errors (8 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/_xmsgs/*.xmsgs?&DataKey=Warning'>11 Warnings (7 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Mar 24 14:49:55 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/_xmsgs/xst.xmsgs?&DataKey=Warning'>7 Warnings (7 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Mar 24 14:50:02 2017</TD><TD ALIGN=LEFT><font color="red"; face="Arial"><b>X </b></font><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/_xmsgs/ngdbuild.xmsgs?&DataKey=Error'>8 Errors (8 new)</A></TD><TD ALIGN=LEFT><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/_xmsgs/ngdbuild.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue Mar 14 18:11:59 2017</TD></TR>
<TR ALIGN=LEFT><TD>Post-Fit Simulation Model Report</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 03/24/2017 - 14:50:02</center>
</BODY></HTML>
\ No newline at end of file
firmware/pc051c_cpld/Multiplexer_xst.xrpt 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Fri Mar 24 14:49:51 2017">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="LD_LIBRARY_PATH"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//lib/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/lib/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/lib:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/lib/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/lib/lin64"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINXD_LICENSE_FILE"/>
<item stringID="value" value="5280@asimov.phy.bris.ac.uk"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="PATH"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE//bin/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/bin/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/util:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/sysgen/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/../../../DocNav:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/bin/lin64:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/common/bin/lin64:/home/phdgc/gopath:/home/phdgc/gopath/bin:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/local/sbin:/usr/bin:/usr/sbin:/usr/libexec/sdcc:/home/phdgc/.local/bin:/home/phdgc/bin:/software/CAD/Mentor/2014_2015/HDS_2013.1b/questasim//bin:/software/CAD/Mentor/2014_2015/HDS_2013.1b/bin:/software/CAD/Altera/13.1/quartus/bin:/software/CAD/Altera/13.1/qprogrammer/bin/:/projects/HEP_Instrumentation/cad/tools"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="LMC_HOME"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64"/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/PlanAhead"/>
</row>
<row stringID="row" value="7">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="/software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Fedora"/>
<item stringID="User_EnvOsrelease" value="Fedora release 24 (Twenty Four)"/>
</item>
<item stringID="User_EnvHost" value="voltar.phy.bris.ac.uk"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i7-2600S CPU @ 2.80GHz"/>
<item stringID="speed" value="2018.481 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="Multiplexer.prj"/>
<item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="Multiplexer"/>
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xbr"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="Multiplexer"/>
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="YES" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="Yes"/>
<item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
<item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="1">
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
</item>
<item dataType="int" stringID="XST_COMPARATORS" value="1"></item>
<item dataType="int" stringID="XST_TRISTATES" value="20">
<item dataType="int" stringID="XST_1BIT_TRISTATE_BUFFER" value="20"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_FINAL_REPORT">
<section stringID="XST_FINAL_RESULTS">
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="Multiplexer.ngr"/>
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="Multiplexer"/>
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
<item stringID="XST_KEEP_HIERARCHY" value="Yes"/>
</section>
<section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="109"/>
</section>
<section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="296">
<item dataType="int" stringID="XST_AND2" value="103"/>
<item dataType="int" stringID="XST_AND3" value="13"/>
<item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="123"/>
<item dataType="int" stringID="XST_OR2" value="41"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="2">
<item dataType="int" stringID="XST_FD" value="2"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="101">
<item dataType="int" stringID="XST_IBUF" value="29"/>
<item dataType="int" stringID="XST_OBUF" value="52"/>
</item>
</section>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="7"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="0"/>
</section>
</application>
</document>
firmware/pc051c_cpld/_ngo/netlist.lst 0 → 100644
View file @ 38654766
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/Multiplexer.ngc 1490366995
firmware/pc051c_cpld/_xmsgs/ngdbuild.xmsgs 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;cpld_led&lt;1&gt;&quot; LOC = &quot;H2&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(103)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;1&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET &quot;cpld_led&lt;1&gt;&quot; LOC = &quot;H2&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(103)]&apos; could not be found and so the Locate constraint will be removed.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD = LVCMOS33 ;&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(103)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;1&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;cpld_led&lt;0&gt;&quot; LOC = &quot;E2&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(104)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;0&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET &quot;cpld_led&lt;0&gt;&quot; LOC = &quot;E2&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(104)]&apos; could not be found and so the Locate constraint will be removed.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD = LVCMOS33 ;&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(104)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;0&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;cpld_led&lt;2&gt;&quot; LOC = &quot;E1&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(105)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;2&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET &quot;cpld_led&lt;2&gt;&quot; LOC = &quot;E1&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(105)]&apos; could not be found and so the Locate constraint will be removed.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD = LVCMOS33 ;&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(105)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;2&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;NET &quot;cpld_led&lt;3&gt;&quot; LOC = &quot;F1&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(106)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;3&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
<msg type="warning" file="ConstraintSystem" num="0" >A target design object for the Locate constraint &apos;&lt;NET &quot;cpld_led&lt;3&gt;&quot; LOC = &quot;F1&quot; |&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(106)]&apos; could not be found and so the Locate constraint will be removed.
</msg>
<msg type="error" file="ConstraintSystem" num="59" delta="new" >Constraint <arg fmt="%s" index="1">&lt;IOSTANDARD = LVCMOS33 ;&gt; [/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.ucf(106)]</arg>: <arg fmt="%s" index="2">NET</arg> &quot;<arg fmt="%s" index="3">cpld_led&lt;3&gt;</arg>&quot; not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
</msg>
</messages>
firmware/pc051c_cpld/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/i2c_deglitch_fsm.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd&quot; into library work</arg>
</msg>
</messages>
firmware/pc051c_cpld/_xmsgs/xst.xmsgs 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="790" delta="new" >&quot;<arg fmt="%s" index="1">/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd</arg>&quot; line <arg fmt="%d" index="2">217</arg>: Index value(s) does not match array range, simulation mismatch.
</msg>
<msg type="warning" file="Xst" num="790" delta="new" >&quot;<arg fmt="%s" index="1">/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd</arg>&quot; line <arg fmt="%d" index="2">219</arg>: Index value(s) does not match array range, simulation mismatch.
</msg>
<msg type="warning" file="Xst" num="790" delta="new" >&quot;<arg fmt="%s" index="1">/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd</arg>&quot; line <arg fmt="%d" index="2">222</arg>: Index value(s) does not match array range, simulation mismatch.
</msg>
<msg type="warning" file="Xst" num="790" delta="new" >&quot;<arg fmt="%s" index="1">/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd</arg>&quot; line <arg fmt="%d" index="2">223</arg>: Index value(s) does not match array range, simulation mismatch.
</msg>
<msg type="warning" file="Xst" num="1306" delta="new" >Output &lt;<arg fmt="%s" index="1">gpio&lt;9:8&gt;</arg>&gt; is never assigned.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">PGood_from_FPGA_i</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="646" delta="new" >Signal &lt;<arg fmt="%s" index="1">s_fpgaPowerEnable</arg>&gt; is assigned but never used. This unconnected signal will be trimmed during the optimization process.
</msg>
</messages>
firmware/pc051c_cpld/fuse.log 0 → 100644
View file @ 38654766
Running: /software/CAD/Xilinx/14.7_64b/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -o /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_isim_beh.exe -prj /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_beh.prj work.tb_i2c_deglitch
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 8
Turning on mult-threading, number of parallel sub-compilation jobs: 16
Determining compilation order of HDL files
Parsing VHDL file "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/../CPLD/src/i2c_deglitch_fsm.vhd" into library work
Parsing VHDL file "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/../CPLD/src/tb_i2c_deglitch.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 97712 KB
Fuse CPU Usage: 950 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package std_logic_arith
Compiling architecture fsm of entity i2c_deglitch [i2c_deglitch_default]
Compiling architecture behavior of entity tb_i2c_deglitch
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 6 VHDL Units
Built simulation executable /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_isim_beh.exe
Fuse Memory Usage: 1191336 KB
Fuse CPU Usage: 1040 ms
GCC CPU Usage: 1540 ms
firmware/pc051c_cpld/fuse.xmsgs 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
firmware/pc051c_cpld/fuseRelaunch.cmd 0 → 100644
View file @ 38654766
-intstyle "ise" -incremental -o "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_isim_beh.exe" -prj "/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_beh.prj" "work.tb_i2c_deglitch"
firmware/pc051c_cpld/iseconfig/Multiplexer.xreport 0 → 100644
View file @ 38654766
This diff is collapsed.
firmware/pc051c_cpld/iseconfig/pc051c_cpld.projectmgr 0 → 100644
View file @ 38654766
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="pc051c_cpld" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Multiplexer - Multiplexer_arch (/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000003a9000000020000000000000000000000000200000064ffffffff000000810000000300000002000003a90000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>Multiplexer - Multiplexer_arch (/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Configure Target Device</ClosedNode>
<ClosedNode>Implement Design/Optional Implementation Tools</ClosedNode>
<ClosedNode>Implement Design/Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Generate Programming File</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000003d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000003d80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Programming File</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000075f000000040101000100000000000000000000000064ffffffff000000810000000000000004000002830000000100000000000000bd00000001000000000000006e0000000100000000000003b10000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/i2c_deglitch_fsm.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>work</ClosedNode>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000123000000010001000100000000000000000000000064ffffffff000000810000000000000001000001230000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>work</CurrentItem>
</ItemView>
<SourceProcessView>000000ff0000000000000002000001360000012001000000060100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
</Project>
<?xml version="1.0" encoding="utf-8"?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="pc051c_cpld" >
<!--This is an ISE project configuration file.-->
</Project>
firmware/pc051c_cpld/isim.cmd 0 → 100644
View file @ 38654766
onerror {resume}
wave add /
run 1000 ns;
firmware/pc051c_cpld/isim.log 0 → 100644
View file @ 38654766
ISim log file
Running: /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/tb_i2c_deglitch_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa)
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
at 200 ns: Note: Waiting for falling edge clk before setting din high (/tb_i2c_deglitch/).
at 200 ns(1): Note: setting Din high (/tb_i2c_deglitch/).
# run 1.00us
# run 1.00us
# exit 0
firmware/pc051c_cpld/isim/isim_usage_statistics.html 0 → 100644
View file @ 38654766
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1040 ms, 1191336 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>10</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>4</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>5</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>3 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.06 sec, 327065 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>
</TABLE>
firmware/pc051c_cpld/isim/tb_i2c_deglitch_isim_beh.exe.sim/isimkernel.log 0 → 100644
View file @ 38654766
Command line:
tb_i2c_deglitch_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 34501
Mon Mar 13 09:11:19 2017
Elaboration Time: 0.04 sec
Current Memory Usage: 253.669 Meg
Total Signals : 10
Total Nets : 6
Total Signal Drivers : 6
Total Blocks : 4
Total Primitive Blocks : 3
Total Processes : 5
Total Traceable Variables : 11
Total Scalar Nets and Variables : 385
Total Simulation Time: 0.06 sec
Current Memory Usage: 328.118 Meg
Tue Mar 14 18:11:58 2017
firmware/pc051c_cpld/isim/tb_i2c_deglitch_isim_beh.exe.sim/work/tb_i2c_deglitch_isim_beh.exe_main.c 0 → 100644
View file @ 38654766
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
char *IEEE_P_3499444699;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
ieee_p_3499444699_init();
work_a_2364958172_2030911003_init();
work_a_0357859748_2372691052_init();
xsi_register_tops("work_a_0357859748_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
IEEE_P_3499444699 = xsi_get_engine_memory("ieee_p_3499444699");
return xsi_run_simulation(argc, argv);
}
firmware/pc051c_cpld/pc051c_cpld.gise 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pc051c_cpld.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="Multiplexer.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Multiplexer.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Multiplexer.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="Multiplexer.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="Multiplexer.ngr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Multiplexer.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="Multiplexer.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Multiplexer.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Multiplexer.xst"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer_ngdbuild.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Multiplexer_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Multiplexer_xst.xrpt"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tb_i2c_deglitch_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="tb_i2c_deglitch_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="tb_i2c_deglitch_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="tb_i2c_deglitch_stx_beh.prj"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1489171013" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1489171013">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1489396268" xil_pn:in_ck="-59338700106216950" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1489396267">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../CPLD/src/Multiplexer_tb.vhd"/>
<outfile xil_pn:name="../CPLD/src/i2c_deglitch_fsm.vhd"/>
<outfile xil_pn:name="../CPLD/src/pc051c_cpld.vhd"/>
<outfile xil_pn:name="../CPLD/src/tb_i2c_deglitch.vhd"/>
</transform>
<transform xil_pn:end_ts="1489171399" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="7320147233388276775" xil_pn:start_ts="1489171399">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1489396268" xil_pn:in_ck="-59338700106216950" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1489396268">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="../CPLD/src/Multiplexer_tb.vhd"/>
<outfile xil_pn:name="../CPLD/src/i2c_deglitch_fsm.vhd"/>
<outfile xil_pn:name="../CPLD/src/pc051c_cpld.vhd"/>
<outfile xil_pn:name="../CPLD/src/tb_i2c_deglitch.vhd"/>
</transform>
<transform xil_pn:end_ts="1489396274" xil_pn:in_ck="-59338700106216950" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-6819532860378678315" xil_pn:start_ts="1489396268">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="tb_i2c_deglitch_beh.prj"/>
<outfile xil_pn:name="tb_i2c_deglitch_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1489396274" xil_pn:in_ck="8007084193972810245" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6918890300558876578" xil_pn:start_ts="1489396274">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="tb_i2c_deglitch_isim_beh.wdb"/>
</transform>
<transform xil_pn:end_ts="1490366980" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1490366980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1490366980" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8111163015149357556" xil_pn:start_ts="1490366980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1490366995" xil_pn:in_ck="-3710800720872503364" xil_pn:name="TRANEXT_xstsynthesize_xbr" xil_pn:prop_ck="-2857206319670813617" xil_pn:start_ts="1490366980">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Multiplexer.lso"/>
<outfile xil_pn:name="Multiplexer.ngc"/>
<outfile xil_pn:name="Multiplexer.ngr"/>
<outfile xil_pn:name="Multiplexer.prj"/>
<outfile xil_pn:name="Multiplexer.stx"/>
<outfile xil_pn:name="Multiplexer.syr"/>
<outfile xil_pn:name="Multiplexer.xst"/>
<outfile xil_pn:name="Multiplexer_xst.xrpt"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1490366995" xil_pn:in_ck="340034899743213582" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="4216875010452136942" xil_pn:start_ts="1490366995">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1490367002" xil_pn:in_ck="8159805456972762127" xil_pn:name="TRAN_ngdbuild" xil_pn:prop_ck="-7850409713972882024" xil_pn:start_ts="1490366995">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="Multiplexer.bld"/>
<outfile xil_pn:name="Multiplexer_ngdbuild.xrpt"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
</transform>
</transforms>
</generated_project>
firmware/pc051c_cpld/pc051c_cpld.xise 0 → 100644
View file @ 38654766
This diff is collapsed.
firmware/pc051c_cpld/pepExtractor.prj 0 → 100644
View file @ 38654766
work "../CPLD/src/i2c_deglitch_fsm.vhd"
firmware/pc051c_cpld/tb_i2c_deglitch_beh.prj 0 → 100644
View file @ 38654766
vhdl work "../CPLD/src/i2c_deglitch_fsm.vhd"
vhdl work "../CPLD/src/tb_i2c_deglitch.vhd"
firmware/pc051c_cpld/tb_i2c_deglitch_stx_beh.prj 0 → 100644
View file @ 38654766
vhdl isim_temp "../CPLD/src/i2c_deglitch_fsm.vhd"
vhdl isim_temp "../CPLD/src/tb_i2c_deglitch.vhd"
firmware/pc051c_cpld/webtalk_pn.xml 0 → 100644
View file @ 38654766
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Fri Mar 24 14:49:40 2017">
<section name="Project Information" visible="false">
<property name="ProjectID" value="FF77E6B8AEE5466897E96DCC239B732F" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/pc051c_cpld/pc051c_cpld.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2016-06-24T09:50:27" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_ImpactProjectFile" value="changed" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_ProjectDescription" value="Code for CPLD on SoLId readout board that multiplexes I2C and SPI busses and handles power sequencing." type="process"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/tb_i2c_deglitch/uut" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_VHDLSourceAnalysisStandard" value="VHDL-200X" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2016-06-24T09:50:27" type="design"/>
<property name="PROP_intWbtProjectID" value="FF77E6B8AEE5466897E96DCC239B732F" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.i2c_deglitch" type="process"/>
<property name="PROP_xcpldFitDesTriMode" value="Float" type="process"/>
<property name="PROP_xcpldFitDesUnused" value="Ground" type="process"/>
<property name="PROP_xilxSynthMaxFanout" value="100000" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="CoolRunner2 CPLDs" type="design"/>
<property name="PROP_DevDevice" value="xc2c256" type="design"/>
<property name="PROP_DevFamilyPMName" value="xbr" type="design"/>
<property name="PROP_DevPackage" value="FT256" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-6" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VHDL" value="4" type="source"/>
</section>
</application>
</document>
firmware/pc051c_cpld/xst/work/hdllib.ref 0 → 100644
View file @ 38654766
EN multiplexer NULL /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd sub00/vhpl00 1490366992
AR multiplexer multiplexer_arch /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd sub00/vhpl01 1490366993
firmware/pc051c_cpld/xst/work/hdpdeps.ref 0 → 100644
View file @ 38654766
V3 3
FL /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd 2017/02/21.14:04:38 P.20131013
EN work/Multiplexer 1490366992 \
FL /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd \
PB ieee/std_logic_1164 1381692176 PB ieee/NUMERIC_STD 1381692181
AR work/Multiplexer/Multiplexer_arch 1490366993 \
FL /projects/HEP_Instrumentation/cad/designs/uob-hep-pc051a/trunk/firmware/CPLD/src/pc051c_cpld.vhd \
EN work/Multiplexer 1490366992
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment