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Euro ADC 65M 14b 40cha hw PUMA-hw
Commit b49dec6a authored by David Cussans's avatar David Cussans
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Checking in files before continuing with changes for version 'c'

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design_files/pc051c_power_filter.cpm 0 → 100644
View file @ b49dec6a
{ Machine generated file created by SPI }
{ Last modified was 19:00:04 Tuesday, March 21, 2017 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/pc051c_power_filter/physical'
design_name 'pc051c_power_filter'
design_library 'uob_hep_pc051a_lib'
library 'uob_hep_pc051a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cninterface' 'cnmemory' 'cnmech' 'cnlinear' 'cds_connectors'
temp_dir 'temp'
cpm_version '16.5'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
EXCLUDE_PPT
INCLUDE_PPT
cdsprop_file ''
log_file ''
physical_path '../www/Docs'
expand_with_errors 'OFF'
session_name 'ProjectMgr3801'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_SIZE '0.050'
DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
HPF_PLOTTER 'Encapsulated PostScript Colour'
HPF_FONT 'native'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc051c_power_filter1.ps'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'JTAGEN' 'JTAG_EN' 'sdi_to_fpga' 'fpga_leds' 'sfp_los'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
HPF_PLOT_PAGESIZE ''
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
repackage 'ON'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
USE_SUBDESIGN 'fmc_tlu_clock_gen'
FORCE_SUBDESIGN 'fmc_tlu_clock_gen' 'ltm9007_8chan_v2' 'trenz_te0712'
GEN_SUBDESIGN
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
f2b_overwrite_constraints 'ON'
b2f_overwrite_constraints 'OFF'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '2'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc051c_power_filter_01.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
show_report 'YES'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/pc051c_power_filter/bom/BOM.rpt'
last_template_file '/projects/HEP_Instrumentation/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Comma ,'
use_filters '0'
last_callout_file ''
last_variant ''
GEN_HIER_BOM '0'
END_BOMHDL
START_VXL
run_directory './worklib/pc051c_power_filter/cfg_verilog/sim1'
END_VXL
START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_VARIANT
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
last_variant_file 'variant.dat'
END_VARIANT
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
design_files/pc051c_toplevel.cpm 0 → 100644
View file @ b49dec6a
{ Machine generated file created by SPI }
{ Last modified was 17:48:41 Tuesday, April 11, 2017 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
START_GLOBAL
view_pcb './worklib/pc051c_toplevel/physical'
design_name 'pc051c_toplevel'
design_library 'uob_hep_pc051a_lib'
library 'uob_hep_pc051a_lib' 'bris_cds_analogue' 'bris_cds_connectors' 'bris_cds_discrete' 'bris_cds_logic' 'bris_cds_memory' 'bris_cds_pld' 'bris_cds_special' 'bris_cds_standard' 'bris_cds_switches' 'cn74lv' 'cn74tiac' 'cn75als' 'cncmos' 'cnconnector' 'cndiscrete' 'cnpassive' 'cnpld' 'cnpower' 'cnspecial' 'cnstandard' 'cnvlsi' 'standard' 'cninterface' 'cnmemory' 'cnmech' 'cnlinear' 'cds_connectors'
temp_dir 'temp'
cpm_version '16.5'
ppt '$BRIS_CDSLIB/cds_analogue/cds_analogue.ptf' '$BRIS_CDSLIB/cds_connectors/cds_connectors.ptf' '$BRIS_CDSLIB/cds_logic/cds_logic.ptf' '$BRIS_CDSLIB/cds_pld/cds_pld.ptf' '$BRIS_CDSLIB/cds_special/cds_special.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnconnector.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cndiscrete.ptf' '$CERN_CDSLIB/lib_psd16.x/concept_libs/pe16/pe_cern_lib/parttables/cnpassive.ptf'
EXCLUDE_PPT
INCLUDE_PPT
cdsprop_file ''
log_file ''
physical_path './worklib/pc051c_toplevel/physical'
expand_with_errors 'OFF'
session_name 'ProjectMgr3801'
END_GLOBAL
START_CONCEPTHDL
LOGIC_GRID_SIZE '0.050'
DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
HPF_PLOTTER 'Encapsulated PostScript Colour'
HPF_FONT 'native'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc051a_toplevel1.ps'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '8'
PAPER_ORIENTATION '2'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
HPF_PLOT_PAGESIZE ''
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
HPF_SCALEFACTOR '0.000000'
SEARCH_HISTORY 'LOL*' 'LOL' 'JTAGEN' 'JTAG_EN' 'sdi_to_fpga'
END_CONCEPTHDL
START_PKGRXL
comp_def_prop 'ALT_SYMBOLS' 'JEDEC_TYPE' 'MERGE_NC_PINS' 'MERGE_POWER_PINS' 'NC_PINS' 'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
comp_inst_prop 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'REUSE_ID' 'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL' 'VOLT_TEMP_SIGNAL_MODEL'
regenerate_physical_net_name 'OFF'
electrical_constraints 'ON'
overwrite_constraints 'OFF'
USE_SUBDESIGN 'fmc_tlu_clock_gen'
FORCE_SUBDESIGN 'fmc_tlu_clock_gen' 'ltm9007_8chan_v2' 'trenz_te0712'
GEN_SUBDESIGN
FILTER_PROPERTY
PASS_PROPERTY
FILTER_CONFLICTING_PROP
f2b_overwrite_constraints 'OFF'
b2f_overwrite_constraints 'OFF'
END_PKGRXL
START_DESIGNSYNC
replace_symbol '0'
etch_removal 'NO'
ignore_fixed 'NO'
create_user_prop 'NO'
run_packager 'YES'
run_netrev 'YES'
backannotate_forward 'NO'
last_board_file 'pc051b_toplevel_166.brd'
run_feedback 'YES'
run_genfeedformat 'YES'
backannotate_feedback 'NO'
show_report 'YES'
END_DESIGNSYNC
START_BOMHDL
last_output_file './worklib/pc051b_toplevel/bom/pc051b_toplevel_1per_line_176.csv'
last_template_file 'Z:/cad/tools/cadence_templates/spreadsheet-format_1per_line.bom'
last_standard_option '1'
last_what_to_output '0'
last_variant_file ''
last_ss_delimiter 'Comma ,'
use_filters '0'
last_callout_file ''
last_variant ''
GEN_HIER_BOM '0'
END_BOMHDL
START_VXL
run_directory './worklib/pc051a_toplevel/cfg_verilog/sim1'
END_VXL
START_ECSET_MODELS
retain_existing_xnets_and_diffpairs 'NO'
END_ECSET_MODELS
START_VARIANT
columns 'REFDES' 'CDS_VAR_STATUS' 'PART_NAME' 'PART_NUMBER'
last_variant_file 'variant.dat'
END_VARIANT
START_ALLEGRO
hdl_padpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/pads' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/pads' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstack_smd' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/padstacks/padstacks/padstack3'
hdl_psmpath '.' 'symbols' '..' '../symbols' '$CADENCE_INST_DIR/share/pcb/pcb_lib/symbols' '$CADENCE_INST_DIR/share/pcb/allegrolib/symbols' '/projects/HEP_Instrumentation/cad/ral_cdslib/lib_psd15.x/symbols' '/projects/HEP_Instrumentation/cad/bris_cdslib/lib_psd14.x/symbols' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/connector' '/projects/HEP_Instrumentation/cad/cern_cdslib/lib_psd16.x/allegro_libs/pe_allegro_lib/symbols/discrete'
hdl_topology_template_path '.' 'templates' '..' '../templates' '$CADENCE_INST_DIR/share/pcb/pcb_lib/templates' '$CADENCE_INST_DIR/share/pcb/allegrolib/templates'
END_ALLEGRO
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