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Euro ADC 65M 14b 40cha hw PUMA-hw
Commit 80b3a4de authored by David Cussans's avatar David Cussans
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design_files/pc051c_i2c_passthrough.cpm
View file @ 80b3a4de
{ Machine generated file created by SPI }
{ Last modified was 14:11:16 Tuesday, March 21, 2017 }
{ Last modified was 11:20:14 Friday, March 24, 2017 }
{ NOTE: Do not modify the contents of this file. If this is regenerated by }
{ SPI, your modifications will be overwritten. }
......@@ -27,21 +27,21 @@ DOC_GRID_SIZE '0.050'
CHECK_VOLTAGE_ON_HDL 'OFF'
PLOT_FIT_TO_PAGE 'ON'
PLOT_FONT 'Arial'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'JTAGEN' 'JTAG_EN' 'sdi_to_fpga' 'fpga_leds' 'sfp_los'
HPF_PLOTTER 'Encapsulated PostScript Colour'
HPF_FONT 'native'
HPF_BATCH 'YES'
HPF_PLOT_FILE_LOCATION '/home/phdgc'
HPF_PLOT_FILE_NAME 'pc051c_i2c_passthrough1.ps'
DONT_SHOW_CM_DLG 'ON'
PRESELECT_FLAG 'ON'
WINDOWSMODE_FLAG 'ON'
SEARCH_HISTORY 'JTAGEN' 'JTAG_EN' 'sdi_to_fpga' 'fpga_leds' 'sfp_los'
PLOTTER_FACILITY 'DEVICE'
PLOT_EDGE_TO_EDGE 'ON'
PAPER_SIZE '8'
PAPER_ORIENTATION '2'
PAPER_SIZE '9'
PAPER_ORIENTATION '1'
PAPER_SOURCE '15'
WPLOTTER_NAME 'Generic PostScript Printer'
WPLOTTER_NAME 'CutePDF Writer'
HPF_PLOT_PAGESIZE ''
HPF_PAGESCALETYPE 'PAGESIZE'
HPF_PAGESIZE 'A4'
......
design_files/worklib/fmc_tlu_clock_gen/packaged/cmbcview.dat 0 → 100644
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design_files/worklib/fmc_tlu_clock_gen/packaged/cmdbview.dat 0 → 100644
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design_files/worklib/fmc_tlu_clock_gen/packaged/compview.dat 0 → 100644
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A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!
J!P:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/fmc_tlu_clock_gen/physical/fmc_tlu_clk_gen_16.brd!Wed Jul 27 12:55:26 2016!-35.0000!-75.0000!180.0000!225.0000!0.0001!millimeters!FMC_TLU_CLOCK_GEN!64.921260 mil!6!UP TO DATE!
S!R2!38!!!RSMD0603!!RSMD0603_1/10W-130,1%!!
S!R5!33!!!RSMD0603!!RSMD0603_1/10W-130,1%!!
S!R3!37!!!RSMD0603!!RSMD0603_1/10W-82,1%!!
S!R6!32!!!RSMD0603!!RSMD0603_1/10W-82,1%!!
S!LK1!34!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK2!30!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK3!12!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!LK4!4!!!1-HOLE!!1-HOLE_0-8-BASE!!
S!QZ1!41!!!OSC_6P_ENDIS_OUTP_OUTN!!BF-100.000MBE-T!!
S!C4!49!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C5!48!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C8!45!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C9!43!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C13!29!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C18!22!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C21!18!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C12!36!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C17!23!!!CAPCERSMDCL2!!CAPCERSMDCL2_0402-100NF,16V_GEN!!
S!C14!28!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C16!25!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C22!17!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C6!47!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C20!20!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-100NF,16V!!
S!C1!55!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C2!54!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C10!42!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C11!40!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C19!21!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C23!16!!!CAPCERSMDCL2!!CAPCERSMDCL2_0603-10UF,6.3V!!
S!C7!46!!!CAPCERSMDCL2!!CAPCERSMDCL2_0805-22UF,6.3V!!
S!C15!26!!!CAPCERSMDCL2!!CAPCERSMDCL2_0805-22UF,6.3V!!
S!C3!53!!!CAPCERSMDCL2!!CAPCERSMDCL2_1210-10UF,10V_GEN!!
S!J2!24!!!CON3P!!CON3P-SIL254D!!
S!J1!27!!!CON3P!!CON3P-SIL254D!!
S!L1!52!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L2!51!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L3!50!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!L4!39!!!FERRITE!!FERRITE_C0805-LI0805H121R-10,LI0805H121R-10!!
S!R8!19!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R14!9!!!RSMD0603!!RSMD0603_1/10W-100,1%!!
S!R1!44!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R9!15!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R10!14!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R12!11!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R19!3!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R11!13!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R13!10!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R15!8!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R16!7!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R17!6!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R18!5!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R20!2!!!RSMD0603!!RSMD0603_1/10W-1K,1%!!
S!R4!35!!!RSMD0603!!RSMD0603_1/10W-XX,1%!!
S!R7!31!!!RSMD0603!!RSMD0603_1/10W-XX,1%!!
S!IC1!1!!!SI5345!!SI5345A-B-GM!!
design_files/worklib/fmc_tlu_clock_gen/packaged/funcview.dat 0 → 100644
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design_files/worklib/fmc_tlu_clock_gen/packaged/netview.dat 0 → 100644
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A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE!
J!P:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/fmc_tlu_clock_gen/physical/fmc_tlu_clk_gen_16.brd!Wed Jul 27 12:55:26 2016 CONSTRAINTS_VIEW_GENERATED!-35.0000!
S!CLK_IN_AC_P!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_in_ac_p!!
S!CLK_IN_AC_N!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_in_ac_n!!
S!CLK9_P!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk9_p!!
S!CLK9_N!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk9_n!!
S!P1V8!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):p1v8!!
S!CLK_OUT_P<0>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(0)!!
S!CLK_OUT_P<1>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(1)!!
S!CLK_OUT_P<2>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(2)!!
S!CLK_OUT_P<3>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(3)!!
S!CLK_OUT_P<4>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(4)!!
S!CLK_OUT_P<5>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(5)!!
S!CLK_OUT_P<6>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(6)!!
S!CLK_OUT_P<7>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(7)!!
S!CLK_OUT_P<8>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_p(8)!!
S!CLK_OUT_N<0>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(0)!!
S!CLK_OUT_N<1>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(1)!!
S!CLK_OUT_N<2>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(2)!!
S!CLK_OUT_N<3>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(3)!!
S!CLK_OUT_N<4>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(4)!!
S!CLK_OUT_N<5>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(5)!!
S!CLK_OUT_N<6>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(6)!!
S!CLK_OUT_N<7>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(7)!!
S!CLK_OUT_N<8>!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_out_n(8)!!
S!CLK_IN_P!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_in_p!!
S!CLK_IN_N!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):clk_in_n!!
S!XB!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):xb!!
S!XA!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):xa!!
S!VDDO_CLK40!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):vddo_clk40!!
S!UNNAMED_3_RSMD0603_I69_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i69_b!!
S!UNNAMED_3_RSMD0603_I68_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i68_b!!
S!UNNAMED_3_RSMD0603_I65_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i65_b!!
S!UNNAMED_3_RSMD0603_I64_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i64_b!!
S!UNNAMED_3_RSMD0603_I62_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i62_b!!
S!UNNAMED_3_RSMD0603_I60_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i60_b!!
S!UNNAMED_3_RSMD0603_I58_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i58_b!!
S!UNNAMED_3_RSMD0603_I57_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_rsmd0603_i57_b!!
S!UNNAMED_3_OSC6PENDISOUTPOUTN_I3!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_osc6pendisoutpoutn_i37_endis!!
S!UNNAMED_3_CAPCERSMDCL2_I45_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i45_b!!
S!UNNAMED_3_CAPCERSMDCL2_I44_B!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):unnamed_3_capcersmdcl2_i44_b!!
S!SDA!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):sda!!
S!SCL!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):scl!!
S!RST*!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):\rst*\!!
S!LOL*!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):\lol*\!!
S!INTR*!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):\intr*\!!
S!VDD_OSC!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):vdd_osc!!
S!VDDA_CLK40!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):vdda_clk40!!
S!VDD_CLK40!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):vdd_clk40!!
S!P3V3!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):p3v3!!
S!GND_SIGNAL!@uob_hep_pc051a_lib.fmc_tlu_clock_gen(sch_1):gnd_signal!!
design_files/worklib/fmc_tlu_clock_gen/packaged/pinview.dat 0 → 100644
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design_files/worklib/fmc_tlu_clock_gen/packaged/pstcmbc.dat 0 → 100644
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design_files/worklib/pc051a_toplevel/physical/allegro.jrl
View file @ 80b3a4de
\t (00:00:08) allegro 16.6-2015 S079 (v16-6-112GH) Windows 32
\t (00:00:08) Journal start - Mon Apr 03 10:43:10 2017
\t (00:00:08) Host=IT018379 User=phdgc Pid=5308 CPUs=8
\t (00:00:08) CmdLine= C:\CAD\Cadence\SPB_16.6\tools\pcb\bin\allegro.exe
\t (00:00:08)
(00:00:09) Searching for nsWare programs v2.62
(00:00:09) NsWare directory found: C:/CAD/Cadence/SPB_16.6/share/local/pcb/skill/nsWare/
(00:00:09) NsWare programs must reside in this directory!
(00:00:09) Loading axlcore.cxt
\t (00:00:11) Opening existing design...
\d (00:00:12) Design opened: Z:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051a_toplevel/physical/pc051b_toplevel_46_temp.brd
\i (00:00:12) trapsize 336
\i (00:00:12) trapsize 330
\i (00:00:12) trapsize 337
\i (00:00:12) trapsize 344
\i (00:00:12) trapsize 298
\i (00:00:12) trapsize 376
\i (00:00:13) trapsize 379
\i (00:00:13) etchedit
\i (00:00:25) pick grid 66.6095 35.7319
\t (00:00:25) last pick: 66.6000 35.7000
\i (00:00:27) zoom out
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out 73.3007 35.2091
\i (00:00:27) trapsize 758
\i (00:00:27) zoom out
\i (00:00:27) setwindow pcb
\i (00:00:27) zoom out 73.3007 35.2090
\t (00:00:27) Grids are drawn 0.2000, 0.2000 apart for enhanced viewability.
\i (00:00:27) trapsize 1516
\i (00:00:28) zoom out
\i (00:00:28) setwindow pcb
\i (00:00:28) zoom out 73.3007 35.2091
\t (00:00:28) Grids are drawn 0.4000, 0.4000 apart for enhanced viewability.
\i (00:00:28) trapsize 3031
\i (00:00:29) roam y 96
\i (00:00:29) roam y 96
\i (00:00:30) roam y 96
\i (00:00:30) roam y 96
\i (00:00:30) roam y 96
\i (00:00:30) roam y 96
\i (00:00:30) roam y -96
\i (00:00:30) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:31) roam y -96
\i (00:00:32) roam y -96
\i (00:00:32) roam y -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:33) roam x -96
\i (00:00:34) roam x -96
\i (00:00:34) roam x -96
\i (00:00:34) roam x -96
\i (00:00:34) roam x -96
\i (00:00:36) zoom out
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 38.3468 58.4846
\t (00:00:36) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:00:36) trapsize 6062
\i (00:00:36) zoom out
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 41.6810 58.4846
\t (00:00:36) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:36) trapsize 12124
\i (00:00:36) zoom out
\i (00:00:36) setwindow pcb
\i (00:00:36) zoom out 152.8620 58.4846
\t (00:00:36) Grids are drawn 3.2000, 3.2000 apart for enhanced viewability.
\i (00:00:36) trapsize 20539
\i (00:00:44) opencd Z:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051a_toplevel/physical/pc051b_toplevel_46.brd
\t (00:00:44) Opening existing design...
\t (00:00:44) Grids are drawn 6.4000, 6.4000 apart for enhanced viewability.
\t (00:00:44) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (00:00:44) trapsize 13954
\d (00:00:44) Design opened: Z:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051a_toplevel/physical/pc051b_toplevel_46.brd
\i (00:00:44) etchedit
\i (00:00:50) open
\i (00:01:10) fillin "Z:\cad\designs\uob-hep-pc051a\trunk\design_files\worklib\pc051b_toplevel\physical\pc051b_toplevel_177.brd"
\i (00:01:10) cd "Z:\cad\designs\uob-hep-pc051a\trunk\design_files\worklib\pc051b_toplevel\physical"
\t (00:01:10) Opening existing design...
\t (00:01:10) Grids are drawn 0.8000, 0.8000 apart for enhanced viewability.
\i (00:01:10) trapsize 1015
\t (00:01:10) Journal end - Mon Apr 03 10:44:12 2017
design_files/worklib/pc051b_toplevel/physical/allegro.jrl
View file @ 80b3a4de
\t (121:49:18) allegro 16.6 S037 (v16-6-112CU) Windows 32
\t (121:49:18) Journal start - Wed Mar 15 11:17:02 2017
\t (121:49:18) Host=IT018379 User=phdgc Pid=7792 CPUs=8
\t (121:49:18) CmdLine= allegro -proj Z:\cad\designs\uob-hep-pc048a\trunk\design_files\/pc048b_mboard.cpm -product PCB_librarian_expert -mpssession phdgc_ProjectMgr58303345 -mpshost IT018379
\t (121:49:18)
\d (121:49:18) Design opened: Z:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051b_toplevel/physical/pc051b_toplevel_177.brd
\i (121:49:19) etchedit
\i (121:49:54) open
\i (121:50:00) fillin "menu_cancel"
\i (121:50:00) etchedit
\i (121:50:01) zoom fit
\i (121:50:01) trapsize 31898
\i (121:50:04) open
\i (121:50:24) fillin "Z:\cad\designs\uob-hep-pc051a\trunk\design_files\worklib\pc051a_toplevel\physical\pc051b_toplevel_46.brd"
\i (121:50:24) cd "Z:\cad\designs\uob-hep-pc051a\trunk\design_files\worklib\pc051a_toplevel\physical"
\t (121:50:24) Opening existing design...
\t (121:50:24) Grids are drawn 1.6000, 1.6000 apart for enhanced viewability.
\i (121:50:24) trapsize 13954
\t (121:50:25) Journal end - Wed Mar 15 11:18:08 2017
\t (00:01:32) allegro 16.6-2015 S079 (v16-6-112GH) Windows 32
\t (00:01:32) Journal start - Wed Apr 12 15:17:45 2017
\t (00:01:32) Host=IT018379 User=phdgc Pid=9168 CPUs=8
\t (00:01:32) CmdLine= C:\CAD\Cadence\SPB_16.6\tools\pcb\bin\allegro.exe
\t (00:01:32)
(00:01:33) Searching for nsWare programs v2.62
(00:01:33) NsWare directory found: C:/CAD/Cadence/SPB_16.6/share/local/pcb/skill/nsWare/
(00:01:33) NsWare programs must reside in this directory!
(00:01:33) Loading axlcore.cxt
\t (00:01:35) Opening existing design...
\d (00:01:36) Design opened: Z:/cad/designs/uob-hep-pc051a/trunk/design_files/worklib/pc051b_toplevel/physical/pc051b_toplevel_177.brd
\i (00:01:38) trapsize 1004
\i (00:01:38) trapsize 986
\i (00:01:38) trapsize 1007
\i (00:01:39) trapsize 888
\i (00:01:39) trapsize 1015
\i (00:01:40) etchedit
\i (00:01:42) zoom fit
\i (00:01:42) trapsize 31898
\i (01:39:43) zoom points
\t (01:39:45) Pick 1st corner of the new window.
\i (01:39:46) pick 118.8216 168.4504
\t (01:39:46) last pick: 118.8216 168.4504
\t (01:39:46) Pick to complete the window.
\i (01:39:47) pick 176.2383 98.2744
\t (01:39:47) last pick: 176.2383 98.2744
\i (01:39:47) trapsize 4853
\i (01:39:47) etchedit
\i (01:39:55) setwindow form.vf_vis
\i (01:39:55) FORM vf_vis 1 pin_colorvisible 1
\i (01:39:58) setwindow pcb
\i (01:39:58) zoom points
\t (01:39:58) Pick 1st corner of the new window.
\i (01:39:59) pick 136.8752 160.2972
\t (01:39:59) last pick: 136.8752 160.2972
\t (01:39:59) Pick to complete the window.
\i (01:40:00) pick 164.8291 144.4760
\t (01:40:00) last pick: 164.8291 144.4760
\i (01:40:00) trapsize 1094
\i (01:40:00) etchedit
\i (01:40:20) drag_start grid 148.0792 152.2662
\i (01:40:20) move
\t (01:40:21) last pick: 149.2500 151.0500
\t (01:40:21) Moving U1 / SN65LVDS1_SOT23-5 / SOT23-5.
\t (01:40:21) Pick new location for the element(s).
\i (01:40:21) drag_stop grid 148.5168 150.7345
\i (01:40:22) etchedit
\i (01:40:23) prepopup 148.4512 150.0561
\i (01:40:25) undo
\i (01:40:25) trapsize 1094
\i (01:40:25) etchedit
\i (24:30:21) setwindow form.find
\i (24:30:21) FORM find find_name LK20
\i (24:30:21) setwindow pcb
\i (24:30:21) trapsize 546
\i (24:30:25) zoom out
\i (24:30:25) setwindow pcb
\i (24:30:25) zoom out 45.4501 451.5448
\i (24:30:25) trapsize 1092
\i (24:30:25) zoom out
\i (24:30:25) setwindow pcb
\i (24:30:25) zoom out 45.4500 451.5449
\i (24:30:25) trapsize 2183
\i (24:30:25) zoom out
\i (24:30:25) setwindow pcb
\i (24:30:25) zoom out 45.4499 451.5449
\i (24:30:25) trapsize 4366
\i (24:30:34) pick grid 45.1880 450.6717
\t (24:30:34) last pick: 45.2000 450.6500
\i (24:30:34) move
\t (24:30:34) last pick: 45.4500 450.7000
\t (24:30:34) Moving LK20 / 1-HOLE_0-8-BASE / 1-HOLE_0-8P.
\t (24:30:34) Pick new location for the element(s).
\i (24:30:35) prepopup 45.1880 450.6717
\i (24:30:37) cancel
\i (24:30:37) etchedit
\i (24:30:40) show element
\i (24:30:41) etchedit
\i (24:30:44) zoom out 1
\i (24:30:44) setwindow pcb
\i (24:30:44) zoom out 63.6137 447.2660
\i (24:30:44) trapsize 8733
\i (24:52:38) exit
\e (24:52:38) Do you want to save the changes you made to pc051b_toplevel_177.brd?
\i (24:52:41) fillin no
\i (24:52:41) setwindow text
\i (24:52:41) close
\t (24:52:41) Journal end - Thu Apr 13 16:08:54 2017
design_files/worklib/pc051c_cpld/chips/chips.prt 0 → 100644
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design_files/worklib/pc051c_cpld/entity/pc.db 0 → 100644
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-- pcdb file, Rev:1.0 written by VAN 31.09-p01 on Feb 21, 2017 14:21:00
design_files/worklib/pc051c_cpld/entity/verilog.v 0 → 100644
View file @ 80b3a4de
// generated by newgenasym Tue Feb 21 14:21:00 2017
module pc051c_cpld (bus_select, clk, csa_to_adc, csb_to_adc, fpga_en1_o,
fpga_power_enable_o, fpga_resin_o, gpio, led, pgnd,
pgood3v3_o, pgood_from_fpga_i, pgood_from_hdmi_i,
pgood_o, por_i, power_switch_high_off,
power_switch_high_on, sck_from_fpga_i, sck_to_adc,
scl_from_fpga_i, scl_to_i2c, sda_i2c, sda_in_to_fpga_o,
sda_out_from_fpga_i, sdi_to_adc, sdi_to_fpga_o,
sdo_from_fpga_i, sdoa_from_adc, sdob_from_adc,
sfp_present, sfp_tx_fault, spi_csn_i, tck, tdi, tdo,
temp_alarm_i, temp_alarm_led_o, tms, vaux, vcc, vccio18,
vccio33);
input [4:0] bus_select;
input clk;
output [7:0] csa_to_adc;
output [7:0] csb_to_adc;
output fpga_en1_o;
output fpga_power_enable_o;
output fpga_resin_o;
input [9:0] gpio;
output [3:0] led;
inout [100:0] pgnd;
output pgood3v3_o;
input pgood_from_fpga_i;
output pgood_from_hdmi_i;
output pgood_o;
input por_i;
input power_switch_high_off;
input power_switch_high_on;
input sck_from_fpga_i;
output [7:0] sck_to_adc;
input scl_from_fpga_i;
output [9:0] scl_to_i2c;
inout [9:0] sda_i2c;
output sda_in_to_fpga_o;
input sda_out_from_fpga_i;
output [7:0] sdi_to_adc;
output sdi_to_fpga_o;
input sdo_from_fpga_i;
input [7:0] sdoa_from_adc;
input [7:0] sdob_from_adc;
output [1:0] sfp_present;
output [1:0] sfp_tx_fault;
input spi_csn_i;
inout tck;
inout tdi;
inout tdo;
input temp_alarm_i;
output temp_alarm_led_o;
inout tms;
inout vaux;
inout [3:0] vcc;
inout [7:0] vccio18;
inout [6:0] vccio33;
initial
begin
end
endmodule
design_files/worklib/pc051c_cpld/entity/vhdl.vhd 0 → 100644
View file @ 80b3a4de
-- generated by newgenasym Tue Feb 21 14:21:00 2017
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity pc051c_cpld is
port (
BUS_SELECT: IN STD_LOGIC_VECTOR (4 DOWNTO 0);
CLK: IN STD_LOGIC;
CSA_TO_ADC: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
CSB_TO_ADC: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
FPGA_EN1_O: OUT STD_LOGIC;
FPGA_POWER_ENABLE_O: OUT STD_LOGIC;
FPGA_RESIN_O: OUT STD_LOGIC;
GPIO: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
LED: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
PGND: INOUT STD_LOGIC_VECTOR (100 DOWNTO 0);
PGOOD3V3_O: OUT STD_LOGIC;
PGOOD_FROM_FPGA_I: IN STD_LOGIC;
PGOOD_FROM_HDMI_I: OUT STD_LOGIC;
PGOOD_O: OUT STD_LOGIC;
POR_I: IN STD_LOGIC;
POWER_SWITCH_HIGH_OFF: IN STD_LOGIC;
POWER_SWITCH_HIGH_ON: IN STD_LOGIC;
SCK_FROM_FPGA_I: IN STD_LOGIC;
SCK_TO_ADC: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
SCL_FROM_FPGA_I: IN STD_LOGIC;
SCL_TO_I2C: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
SDA_I2C: INOUT STD_LOGIC_VECTOR (9 DOWNTO 0);
SDA_IN_TO_FPGA_O: OUT STD_LOGIC;
SDA_OUT_FROM_FPGA_I: IN STD_LOGIC;
SDI_TO_ADC: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
SDI_TO_FPGA_O: OUT STD_LOGIC;
SDO_FROM_FPGA_I: IN STD_LOGIC;
SDOA_FROM_ADC: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SDOB_FROM_ADC: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SFP_PRESENT: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
SFP_TX_FAULT: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
SPI_CSN_I: IN STD_LOGIC;
TCK: INOUT STD_LOGIC;
TDI: INOUT STD_LOGIC;
TDO: INOUT STD_LOGIC;
TEMP_ALARM_I: IN STD_LOGIC;
TEMP_ALARM_LED_O: OUT STD_LOGIC;
TMS: INOUT STD_LOGIC;
VAUX: INOUT STD_LOGIC;
VCC: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
VCCIO18: INOUT STD_LOGIC_VECTOR (7 DOWNTO 0);
VCCIO33: INOUT STD_LOGIC_VECTOR (6 DOWNTO 0));
end pc051c_cpld;
design_files/worklib/pc051c_cpld/metadata/pdv_validation.txt 0 → 100644
View file @ 80b3a4de
SPLBPD-170,Cell 'pc051c_cpld':Pin(s) PGND<101>,PGND<102> is (are) not present in any package or symbol. You can choose Pins - Add from the Package Pin page and delete these pins. If the HAS_FIXED_SIZE value has been reduced, reload the part.,Warning
design_files/worklib/pc051c_cpld/metadata/pinlist.txt 0 → 100644
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design_files/worklib/pc051c_cpld/metadata/revision.dat 0 → 100644
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(Cell pc051c_cpld
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.10)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 02/21/17,11:58:17)
(User phdgc)
(Path uob_hep_pc051a_lib.pc051c_cpld)
)
)
(Views
(View Symbol
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.5)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 02/21/17,11:58:17)
(User phdgc)
(Path uob_hep_pc051a_lib.pc051c_cpld)
)
)
(Symbols 1
(Symbol sym_1
(Symbol_Type Normal)
(Max_Size 0)
(Checksum 00000000fe367cb4)
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.5)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 02/21/17,11:58:17)
(User phdgc)
(Path uob_hep_pc051a_lib.pc051c_cpld)
)
)
)
)
(Checksum 000000001e0003e5)
)
(View Chips
(Checksum 0000000085ad3331)
(Primitives 1
(Primitive PC051C_CPLD
(RevisionInfoBlock
(Baselined 0)
(Revision 0.0.4)
(ModificationStatus NULL)
(Status Created)
(ErrorStatus 0)
(CreateInfo
(Time 02/21/17,11:58:17)
(User phdgc)
(Path uob_hep_pc051a_lib.pc051c_cpld)
)
)
(LogicalPhysicalPartRelation
(LogicalPart PC051C_CPLD
(PackType PC051C_CPLD)
)
)
(Packages 1
(FunctionGroups 1
(FunctionGroup 1[1]
(Linkages
(Linkage Symbol
(Name sym_1)
)
)
)
)
(Linkages
(DefaultFootPrint
(Name BGA256T16_100)
)
)
)
)
)
)
(Checksum 000000001d8003ab)
)
(VersionInfoBlock
(ToolName PDV)
(Version 16.6-S051 (v16-6-112ED))
(License PCB_librarian_expert)
)
(Checksum 000000001bd103a4)
)
design_files/worklib/pc051c_cpld/sym_1/symbol.css 0 → 100644
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design_files/worklib/pc051c_power_filter/cfg_package/expand.cfg 0 → 100644
View file @ 80b3a4de
config pc051c_power_filter;
design uob_hep_pc051a_lib.pc051c_power_filter:sch_1;
liblist uob_hep_pc051a_lib, bris_cds_analogue, bris_cds_connectors, bris_cds_discrete, bris_cds_logic, bris_cds_memory, bris_cds_pld, bris_cds_special, bris_cds_standard, bris_cds_switches, cn74lv, cn74tiac, cn75als, cncmos, cnconnector, cndiscrete, cnpassive, cnpld, cnpower, cnspecial, cnstandard, cnvlsi, standard, cninterface, cnmemory, cnmech, cnlinear, cds_connectors;
viewlist chips, pic_1, picopt_1, sch_1, schematic, entity, functional;
stoplist chips;
endconfig
design_files/worklib/pc051c_power_filter/sch_1/master.tag 0 → 100644
View file @ 80b3a4de
page1.csa
pc051c_power_filter.xcon
pc051c_power_filter.dcf
design_files/worklib/pc051c_power_filter/sch_1/module_order.dat 0 → 100644
View file @ 80b3a4de
Version 15.0
START_MODULEORDER
@uob_hep_pc051a_lib.pc051c_power_filter(sch_1) 0 1 1 1 0
END_MODULEORDER
design_files/worklib/pc051c_power_filter/sch_1/page1.cpc 0 → 100644
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design_files/worklib/pc051c_power_filter/sch_1/page1.csa 0 → 100644
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design_files/worklib/pc051c_power_filter/sch_1/page1.csv 0 → 100644
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design_files/worklib/pc051c_power_filter/sch_1/pc.db 0 → 100644
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firmware/CPLD/src/pc051b_cpld.vhd
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