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Created with Raphaël 2.2.024Apr231615109854328Mar4127Feb26121118Jan1723Nov2221191615132Oct12Sep28Aug24Jul1912109514Jun422May141110827Apr1029Mar272221201916151312987652129Feb282724232221201716151413109863226Jan2518171613105Dec20Oct191812Sep542131Aug3029242322191715121110985432129Jul281222Jun212014109631May266428Apr212019181716151312119876api: remove opaque types for structuresapi: expose return value of cycle close under C++tools: rename firmware load tools to eb-{get,put}api: begin EB software refactoring (breaks API/ABI compat)eb-upload: failure to seek is fatalstablestabletools: improve bounds checkingapi: rename eb-load/store to eb-upload/download -- less confusingapi device: cache fcntl flags => less syscalls => faster transferseb-load/store: LFS supportapi: adjust old test program to expect etherbone header in treeload/store: do not use global variables => broke eb-storeeb2: pop FIFOs only when both readyapi: gitignore new test binaryusb: wrong cdc_acm feature reported -- breaks windowseb2: parameterize FIFO deptheb2: cover the gap between strobe and busyeb2: when TX is being dropped, of course we don't stallapi: integrate/update the old test programapi: include old test program from Marcuseb2: fix existing stream conversioneb2: use tags to control TX cycle line and sync error shift registereb2: fixup inter-operation cycle line controleb2: dpram inputs are registeredeb2: less bad fifo adaptereb2: first hash at size converting fifoapi: unset non-blocking when requestedeb2: fix bug where wishbone master did not hold stb on stalleb2: fix bug pushing all access to config spaceeb2: discard writes consistentlyeb2: fix tx mux hangeb2: add protection against faulty slaveseb2: fix bugs found by quartuseb2: integrate new FSM with top componentseb2: appease modelsim and fine-tune flow control logicstatemachine almost completeeb2: don't push zeros on writes; leave that to the fsm using passeb2: modelsim is happyeb2: all the TX path is thereeb2: first few FIFOs and muxinterfaces for V2