On falling edge of RX cycle line, push a request to the tag FIFO to lower TX.
Lower the WB master cycle line as soon as no inflight operations.

... split wbm fifo from master outputs
... also named most 32 bit vectors

The datasheet is wrong for tXFLG on read and write
  => use 80ns instead of 70ns
Also use a single register input for fd_i
  => makes fast register input mode possible for the pins