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Commit fb7a780a authored by Mathias Kreider's avatar Mathias Kreider
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......@@ -397,13 +397,13 @@ begin
else
-- RX cycle line lowered before all words were transferred
if ((s_EB_RX_byte_cnt < s_EB_packet_length) AND (s_rx_fifo_empty = '1') AND EB_RX_i.CYC = '0') then
if ((s_state_RX /= ERROR) AND (s_state_RX /= IDLE) AND (s_EB_RX_byte_cnt < s_EB_packet_length) AND (s_rx_fifo_empty = '1') AND EB_RX_i.CYC = '0') then
report "EB: Packet was shorter than specified by UDP length field" severity note;
--ERROR: -- RX cycle line lowered before all words were transferred
s_state_RX <= ERROR;
s_state_TX <= IDLE;
--
elsif((s_EB_RX_byte_cnt > s_EB_packet_length) AND ((s_state_RX /= IDLE) AND (s_state_RX /= EB_HDR_REC))) then
elsif((s_EB_RX_byte_cnt > s_EB_packet_length) AND ((s_state_RX /= ERROR) AND (s_state_RX /= IDLE) AND (s_state_RX /= EB_HDR_REC))) then
report "EB: Packet was longer than specified by UDP length field" severity note;
s_state_RX <= ERROR;
s_state_TX <= IDLE;
......@@ -609,9 +609,10 @@ begin
s_EB_TX_HDR <= init_EB_HDR;
PROBE_ID <= X"1337BEEF";
s_EB_TX_CUR_CYCLE <= to_EB_CYC(test);
s_EB_TX_CUR_CYCLE <= INIT_EB_CYC;
s_EB_RX_CUR_CYCLE <= INIT_EB_CYC;
s_EB_TX_base_wr_adr<= (others => '0');
s_EB_RX_CUR_CYCLE <= to_EB_CYC(test);
s_WB_CYC <= '0';
s_EB_RX_ACK <= '0';
......@@ -661,7 +662,8 @@ begin
case s_state_RX is
when IDLE => s_EB_packet_length <= (others => '0');
when IDLE => s_EB_RX_CUR_CYCLE <= INIT_EB_CYC;
s_EB_packet_length <= (others => '0');
s_status_clr <= '1';
......@@ -797,6 +799,7 @@ begin
when ERROR => report "EB: ERROR" severity warning;
s_WB_CYC <= '0';
s_EB_packet_length <= (others => '0');
s_tx_fifo_clr <= '1';
s_rx_fifo_clr <= '1';
end case;
......
......@@ -192,6 +192,10 @@ return EB_HDR;
function TO_EB_CYC(X : std_logic_vector)
return EB_CYC;
function INIT_EB_CYC
return EB_CYC;
function TO_STD_LOGIC_VECTOR(X : EB_CYC)
return std_logic_vector;
......@@ -396,6 +400,25 @@ return EB_CYC is
return tmp;
end function TO_EB_CYC;
function INIT_EB_CYC
return EB_CYC is
variable tmp : EB_CYC;
begin
tmp.BCA_CFG := '0';
tmp.RCA_CFG := '0';
tmp.RD_FIFO := '0';
tmp.RESERVED1 := '0';
tmp.DROP_CYC := '1';
tmp.WCA_CFG := '0';
tmp.WR_FIFO := '0';
tmp.RESERVED2 := '0';
tmp.RESERVED3 := (others => '0');
tmp.WR_CNT := (others => '0');
tmp.RD_CNT := (others => '0');
return tmp;
end function INIT_EB_CYC;
function TO_STD_LOGIC_VECTOR(X : EB_CYC)
return std_logic_vector is
variable tmp : std_logic_vector(31 downto 0) := (others => '0');
......
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