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Commit d4a97235 authored by Mathias Kreider's avatar Mathias Kreider
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long overdue clean up work done. 

thx to Weibin for pointing out bug in eb_config
parent 5bc03c4e
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hdl/eb_slave_core/eb_config.vhd
+ 142
− 160
View file @ d4a97235
......@@ -31,177 +31,159 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
entity eb_config is
generic(
g_sdb_address : std_logic_vector(63 downto 0));
port(
clk_i : in std_logic; --clock
nRST_i : in std_logic;
status_i : in std_logic;
status_en : in std_logic;
status_clr : in std_logic;
my_mac_o : out std_logic_vector(6*8-1 downto 0);
my_ip_o : out std_logic_vector(4*8-1 downto 0);
my_port_o : out std_logic_vector(2*8-1 downto 0);
local_slave_o : out t_wishbone_slave_out;
local_slave_i : in t_wishbone_slave_in; --! local Wishbone master lines
eb_slave_o : out t_wishbone_slave_out; --! EB Wishbone slave lines
eb_slave_i : in t_wishbone_slave_in
entity eb_config is
generic(
g_sdb_address : std_logic_vector(63 downto 0));
port(
clk_i : in std_logic; --clock
nRST_i : in std_logic;
status_i : in std_logic;
status_en : in std_logic;
status_clr : in std_logic;
my_mac_o : out std_logic_vector(6*8-1 downto 0);
my_ip_o : out std_logic_vector(4*8-1 downto 0);
my_port_o : out std_logic_vector(2*8-1 downto 0);
local_slave_o : out t_wishbone_slave_out;
local_slave_i : in t_wishbone_slave_in; --! local Wishbone master lines
eb_slave_o : out t_wishbone_slave_out; --! EB Wishbone slave lines
eb_slave_i : in t_wishbone_slave_in
);
end eb_config;
architecture behavioral of eb_config is
subtype dword is std_logic_vector(31 downto 0);
type mem is array (0 to 2) of dword ;
signal my_mem : mem;
signal eb_adr : natural;
signal local_adr : natural;
signal local_write_reg : std_logic_vector(31 downto 0);
signal status_reg : std_logic_vector(63 downto 0);
signal p_auto_cfg : std_logic_vector(63 downto 0);
signal my_mac : std_logic_vector(6*8-1 downto 0);
signal my_ip : std_logic_vector(4*8-1 downto 0);
signal my_port : std_logic_vector(2*8-1 downto 0);
constant c_my_default_mac : std_logic_vector(6*8-1 downto 0) := x"D15EA5EDBEEF";
constant c_my_default_ip : std_logic_vector(4*8-1 downto 0) := x"C0A80064";
constant c_my_default_port : std_logic_vector(2*8-1 downto 0) := x"EBD0";
subtype dword is std_logic_vector(31 downto 0);
type mem is array (0 to 2) of dword;
signal my_mem : mem;
signal eb_adr : natural;
signal local_adr : natural;
signal local_write_reg : std_logic_vector(31 downto 0);
signal status_reg : std_logic_vector(63 downto 0);
signal p_auto_cfg : std_logic_vector(63 downto 0);
signal my_mac : std_logic_vector(6*8-1 downto 0);
signal my_ip : std_logic_vector(4*8-1 downto 0);
signal my_port : std_logic_vector(2*8-1 downto 0);
constant c_my_default_mac : std_logic_vector(6*8-1 downto 0) := x"D15EA5EDBEEF";
constant c_my_default_ip : std_logic_vector(4*8-1 downto 0) := x"C0A80064";
constant c_my_default_port : std_logic_vector(2*8-1 downto 0) := x"EBD0";
begin
eb_adr <= to_integer(unsigned(eb_slave_i.ADR(7 downto 2)) & "00");
local_adr <= to_integer(unsigned(local_slave_i.ADR(7 downto 2)) & "00");
my_mac_o <= my_mac;
my_ip_o <= my_ip;
my_port_o <= my_port;
eb_adr <= to_integer(unsigned(eb_slave_i.ADR(7 downto 2)) & "00");
local_adr <= to_integer(unsigned(local_slave_i.ADR(7 downto 2)) & "00");
my_mac_o <= my_mac;
my_ip_o <= my_ip;
my_port_o <= my_port;
local_slave_o.STALL <= eb_slave_i.CYC;
local_slave_o.INT <= '0';
local_slave_o.RTY <= '0';
local_slave_o.STALL <= eb_slave_i.CYC;
local_slave_o.INT <= '0';
local_slave_o.RTY <= '0';
eb_if : process (clk_i)
eb_if : process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(nRSt_i = '0') then
eb_slave_o <= (
ACK => '0',
ERR => '0',
RTY => '0',
STALL => '0',
INT => '0',
DAT => (others => '0'));
local_slave_o.ACK <= '0';
local_slave_o.ERR <= '0';
local_slave_o.DAT <= (others => '0');
my_ip <= c_my_default_ip;
my_mac <= c_my_default_mac;
my_port <= c_my_default_port;
p_auto_cfg <= g_sdb_address;
else
eb_slave_o.ACK <= eb_slave_i.CYC AND eb_slave_i.STB;
if(eb_slave_i.STB = '1' AND eb_slave_i.CYC = '1') then
if(eb_slave_i.WE ='1') then
case eb_adr is
when 0 => null;
when 16 => my_mac(47 downto 16) <= eb_slave_i.DAT(31 downto 0);
when 20 => my_mac(15 downto 0) <= eb_slave_i.DAT(31 downto 16);
when 24 => my_ip <= eb_slave_i.DAT;
when 28 => my_port <= eb_slave_i.DAT(31 downto 16);
when others => null;
end case;
else
case eb_adr is
when 0 => eb_slave_o.DAT <= status_reg(63 downto 32);
when 4 => eb_slave_o.DAT <= status_reg(31 downto 0);
when 8 => eb_slave_o.DAT <= p_auto_cfg(63 downto 32);
when 12 => eb_slave_o.DAT <= p_auto_cfg(31 downto 0);
when 16 => eb_slave_o.DAT <= my_mac(47 downto 16);
when 20 => eb_slave_o.DAT <= (my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16)));
when 24 => eb_slave_o.DAT <= my_ip;
when 28 => eb_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16));
when others => eb_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
end if;
local_slave_o.ACK <= local_slave_i.STB AND local_slave_i.CYC AND NOT eb_slave_i.CYC;
if(local_slave_i.STB = '1' AND local_slave_i.CYC = '1' AND eb_slave_i.CYC = '0') then
if(local_slave_i.WE ='1') then
local_write_reg <= local_slave_i.DAT;
case local_adr is
when 8 => p_auto_cfg(63 downto 32) <= local_write_reg;
when 12 => p_auto_cfg(31 downto 0) <= local_write_reg;
when 16 => my_mac(47 downto 16) <= local_write_reg(31 downto 0);
when 20 => my_mac(15 downto 0) <= local_write_reg(31 downto 16);
when 24 => my_ip <= local_write_reg;
when 28 => my_port <= local_write_reg(31 downto 16);
when others => null;
end case;
else
case local_adr is
when 0 => local_slave_o.DAT <= status_reg(63 downto 32);
when 4 => local_slave_o.DAT <= status_reg(31 downto 0);
when 8 => local_slave_o.DAT <= p_auto_cfg(63 downto 32);
when 12 => local_slave_o.DAT <= p_auto_cfg(31 downto 0);
when 16 => local_slave_o.DAT <= my_mac(47 downto 16);
when 20 => local_slave_o.DAT <= my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16));
when 24 => local_slave_o.DAT <= my_ip;
when 28 => local_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16)) ;
when others => local_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
end if;
end if;
end if;
end process;
status_reg_sh : process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(nRSt_i = '0') then
status_reg <= (others => '0');
else
if(status_clr = '1') then
--status_reg <= (others => '0');
elsif(status_en = '1') then
status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
end if;
end if;
end if;
end process;
if (clk_i'event and clk_i = '1') then
if(nRSt_i = '0') then
eb_slave_o <= (
ACK => '0',
ERR => '0',
RTY => '0',
STALL => '0',
INT => '0',
DAT => (others => '0'));
local_slave_o.ACK <= '0';
local_slave_o.ERR <= '0';
local_slave_o.DAT <= (others => '0');
my_ip <= c_my_default_ip;
my_mac <= c_my_default_mac;
my_port <= c_my_default_port;
p_auto_cfg <= g_sdb_address;
else
--EB Side
eb_slave_o.ACK <= eb_slave_i.CYC and eb_slave_i.STB;
if(eb_slave_i.STB = '1' and eb_slave_i.CYC = '1') then
if(eb_slave_i.WE = '1') then
case eb_adr is
when 0 => null;
when 16 => my_mac(47 downto 16) <= eb_slave_i.DAT(31 downto 0);
when 20 => my_mac(15 downto 0) <= eb_slave_i.DAT(31 downto 16);
when 24 => my_ip <= eb_slave_i.DAT;
when 28 => my_port <= eb_slave_i.DAT(31 downto 16);
when others => null;
end case;
else
case eb_adr is
when 0 => eb_slave_o.DAT <= status_reg(63 downto 32);
when 4 => eb_slave_o.DAT <= status_reg(31 downto 0);
when 8 => eb_slave_o.DAT <= p_auto_cfg(63 downto 32);
when 12 => eb_slave_o.DAT <= p_auto_cfg(31 downto 0);
when 16 => eb_slave_o.DAT <= my_mac(47 downto 16);
when 20 => eb_slave_o.DAT <= (my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16)));
when 24 => eb_slave_o.DAT <= my_ip;
when 28 => eb_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16));
when others => eb_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
end if;
--Local Side
local_slave_o.ACK <= local_slave_i.STB and local_slave_i.CYC and not eb_slave_i.CYC;
if(local_slave_i.STB = '1' and local_slave_i.CYC = '1' and eb_slave_i.CYC = '0') then
if(local_slave_i.WE = '1') then
case local_adr is
when 8 => p_auto_cfg(63 downto 32) <= local_slave_i.DAT;
when 12 => p_auto_cfg(31 downto 0) <= local_slave_i.DAT;
when 16 => my_mac(47 downto 16) <= local_slave_i.DAT(31 downto 0);
when 20 => my_mac(15 downto 0) <= local_slave_i.DAT(31 downto 16);
when 24 => my_ip <= local_slave_i.DAT;
when 28 => my_port <= local_slave_i.DAT(31 downto 16);
when others => null;
end case;
else
case local_adr is
when 0 => local_slave_o.DAT <= status_reg(63 downto 32);
when 4 => local_slave_o.DAT <= status_reg(31 downto 0);
when 8 => local_slave_o.DAT <= p_auto_cfg(63 downto 32);
when 12 => local_slave_o.DAT <= p_auto_cfg(31 downto 0);
when 16 => local_slave_o.DAT <= my_mac(47 downto 16);
when 20 => local_slave_o.DAT <= my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16));
when 24 => local_slave_o.DAT <= my_ip;
when 28 => local_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16));
when others => local_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
end if;
end if;
end if;
end process;
status_reg_sh : process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(nRSt_i = '0') then
status_reg <= (others => '0');
else
if(status_clr = '1') then
--status_reg <= (others => '0');
elsif(status_en = '1') then
status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
end if;
end if;
end if;
end process;
end behavioral;
hdl/eb_slave_core/eb_main_fsm.vhd
+ 605
− 641
View file @ d4a97235
This diff is collapsed.
hdl/eb_slave_core/eb_rx_ctrl.vhd
+ 292
− 368
View file @ d4a97235
This diff is collapsed.
hdl/eb_slave_core/eb_tx_ctrl.vhd
+ 207
− 272
View file @ d4a97235
......@@ -39,40 +39,31 @@ use work.eb_hdr_pkg.all;
use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all;
entity EB_TX_CTRL is
port(
clk_i : in std_logic;
nRst_i : in std_logic;
--Eth MAC WB Streaming signals
wb_slave_i : in t_wishbone_slave_in;
wb_slave_o : out t_wishbone_slave_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
reply_MAC_i : in std_logic_vector(6*8-1 downto 0);
reply_IP_i : in std_logic_vector(4*8-1 downto 0);
reply_Port_i : in std_logic_vector(2*8-1 downto 0);
clk_i : in std_logic;
nRst_i : in std_logic;
TOL_i : in std_logic_vector(2*8-1 downto 0);
payload_len_i : in std_logic_vector(2*8-1 downto 0);
my_mac_i : in std_logic_vector(6*8-1 downto 0);
my_vlan_i : in std_logic_vector(2*8-1 downto 0);
my_ip_i : in std_logic_vector(4*8-1 downto 0);
my_port_i : in std_logic_vector(2*8-1 downto 0);
silent_i : in std_logic;
valid_i : in std_logic
--Eth MAC WB Streaming signals
wb_slave_i : in t_wishbone_slave_in;
wb_slave_o : out t_wishbone_slave_out;
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out;
reply_MAC_i : in std_logic_vector(6*8-1 downto 0);
reply_IP_i : in std_logic_vector(4*8-1 downto 0);
reply_Port_i : in std_logic_vector(2*8-1 downto 0);
TOL_i : in std_logic_vector(2*8-1 downto 0);
payload_len_i : in std_logic_vector(2*8-1 downto 0);
my_mac_i : in std_logic_vector(6*8-1 downto 0);
my_vlan_i : in std_logic_vector(2*8-1 downto 0);
my_ip_i : in std_logic_vector(4*8-1 downto 0);
my_port_i : in std_logic_vector(2*8-1 downto 0);
silent_i : in std_logic;
valid_i : in std_logic
);
end entity;
......@@ -146,69 +137,52 @@ port(
signal conv_A : t_wishbone_slave_out; --!
-- main FSM
type st is (IDLE, CALC_CHKSUM, WAIT_SEND_REQ, PREP_ETH, ETH, IPV4, UDP, HDR_SEND, PAYLOAD_SEND, PADDING, WAIT_IFGAP, ERROR);
signal state : st := IDLE;
signal ETH_TX : ETH_HDR;
signal IPV4_TX : IPV4_HDR;
signal UDP_TX : UDP_HDR;
signal TX_HDR_slv : std_logic_vector(c_IPV4_HLEN*8 -1 downto 0);
type st is (IDLE, CALC_CHKSUM, WAIT_SEND_REQ, PREP_ETH, ETH, IPV4, UDP, HDR_SEND, PAYLOAD_SEND, PADDING, WAIT_IFGAP, ERRORS);
signal state : st := IDLE;
signal ETH_TX : ETH_HDR;
signal IPV4_TX : IPV4_HDR;
signal UDP_TX : UDP_HDR;
signal TX_HDR_slv : std_logic_vector(c_IPV4_HLEN*8 -1 downto 0);
--shift register output and control signals
signal byte_count : natural range 0 to 1600;
signal counter_comp : natural range 0 to 1600;
signal s_timeout_cnt : unsigned(14 downto 0);
alias a_timeout : unsigned(0 downto 0) is s_timeout_cnt(s_timeout_cnt'left downto s_timeout_cnt'left);
signal eop : natural range 0 to 1600;
signal s_sh_hdr_en : std_logic;
signal ld_hdr : std_logic;
signal chksum_empty : std_logic;
--signal chksum_full : std_logic;
signal byte_count : natural range 0 to 1600;
signal counter_comp : natural range 0 to 1600;
signal s_timeout_cnt : unsigned(14 downto 0);
alias a_timeout : unsigned(0 downto 0) is s_timeout_cnt(s_timeout_cnt'left downto s_timeout_cnt'left);
signal eop : natural range 0 to 1600;
signal s_sh_hdr_en : std_logic;
signal ld_hdr : std_logic;
signal chksum_empty : std_logic;
-- forking the bus
type stmux is (HEADER, PAYLOAD, PADDING, NONE);
signal state_mux : stmux := HEADER;
signal wb_payload_stall_o : t_wishbone_slave_out;
signal stalled : std_logic;
signal state_mux : stmux := HEADER;
signal wb_payload_stall_o : t_wishbone_slave_out;
signal stalled : std_logic;
-- IP checksum generator
signal p_chk_vals : std_logic_vector(95 downto 0);
signal s_chk_vals : std_logic_vector(15 downto 0);
signal IP_chk_sum : std_logic_vector(15 downto 0);
signal sh_chk_en : std_logic;
signal calc_chk_en : std_logic;
signal ld_p_chk_vals : std_logic; --parallel load
signal chksum_done : std_logic;
signal s_src_o : t_wrf_source_out;
signal s_src_hdr_o : t_wrf_source_out;
signal p_chk_vals : std_logic_vector(95 downto 0);
signal s_chk_vals : std_logic_vector(15 downto 0);
signal IP_chk_sum : std_logic_vector(15 downto 0);
signal sh_chk_en : std_logic;
signal calc_chk_en : std_logic;
signal ld_p_chk_vals : std_logic; --parallel load
signal chksum_done : std_logic;
signal s_src_o : t_wrf_source_out;
signal s_src_hdr_o : t_wrf_source_out;
signal s_src_payload_o : t_wrf_source_out;
signal s_src_padding_o : t_wrf_source_out;
signal payload_cyc : std_logic;
signal hdr_wait : std_logic;
signal hdr_done : std_logic;
signal s_ETH_end : natural range 12 to 16;
signal nRst_conv : std_logic;
signal conv_reset : std_logic;
signal payload_cyc : std_logic;
signal hdr_wait : std_logic;
signal hdr_done : std_logic;
signal s_ETH_end : natural range 12 to 16;
signal nRst_conv : std_logic;
signal conv_reset : std_logic;
begin
count_tx_bytes : process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -218,17 +192,15 @@ begin
if(s_src_o.stb = '1' and s_src_o.cyc = '1' and src_i.stall = '0') then
byte_count <= byte_count + 2;
end if;
end if;
end if;
end process;
nRst_conv <= nRst_i AND NOT conv_reset;
-- source output mapping to source output signals
src_o.cyc <= '0' when state_mux = NONE
else '1';
src_o.stb <= s_src_o.stb;
src_o.dat <= s_src_o.dat;
src_o.sel <= "11";
......@@ -237,16 +209,15 @@ src_o.we <= '1';
-- source mux
MUX_TX : with state_mux select
s_src_o <= s_src_hdr_o when HEADER,
s_src_payload_o when PAYLOAD,
s_src_padding_o when PADDING,
s_src_padding_o when others;
s_src_o <= s_src_hdr_o when HEADER,
s_src_payload_o when PAYLOAD,
s_src_padding_o when PADDING,
s_src_padding_o when others;
-- wb_slave mux
MUX_WB : with state_mux select
wb_slave_o.STALL <= conv_A.STALL when PAYLOAD,
'1' when others;
'1' when others;
wb_slave_o.ACK <= conv_A.ACK;
wb_slave_o.ERR <= conv_A.ERR;
......@@ -254,13 +225,11 @@ wb_slave_o.RTY <= '0';
wb_slave_o.INT <= '0';
wb_slave_o.DAT <= (others => '0');
s_sh_hdr_en <= s_src_hdr_o.cyc and s_src_hdr_o.stb and not src_i.stall;
PL_WAIT : with state_mux select
payload_cyc <= wb_slave_i.CYC when PAYLOAD,
'0' when others;
'0' when others;
s_sh_hdr_en <= s_src_hdr_o.cyc and s_src_hdr_o.stb and not src_i.stall;
shift_hdr_chk_sum : piso_flag generic map( 96, 16, 1)
port map ( d_i => p_chk_vals,
......@@ -269,8 +238,8 @@ port map ( d_i => p_chk_vals,
nRST_i => nRST_i,
en_i => sh_chk_en,
ld_i => ld_p_chk_vals,
full_o => open,
empty_o => chksum_empty
full_o => open,
empty_o => chksum_empty
);
p_chk_vals <= x"C511" & IPV4_TX.SRC & IPV4_TX.DST & IPV4_TX.TOL;
......@@ -282,27 +251,16 @@ chksum_generator: EB_checksum port map ( clk_i => clk_i,
done_o => chksum_done,
sum_o => IP_chk_sum );
Shift_out: piso_flag generic map (c_IPV4_HLEN*8, 16, 0)
port map ( d_i => TX_HDR_slv,
q_o => s_src_hdr_o.DAT,
clk_i => clk_i,
nRST_i => nRST_i,
en_i => s_sh_hdr_en,
ld_i => ld_hdr,
full_o => open,
empty_o => open
);
port map ( d_i => TX_HDR_slv,
q_o => s_src_hdr_o.DAT,
clk_i => clk_i,
nRST_i => nRST_i,
en_i => s_sh_hdr_en,
ld_i => ld_hdr,
full_o => open,
empty_o => open);
-- convert streaming input from 16 to 32 bit data width
uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
g_adr_width_B => 2,
......@@ -334,10 +292,10 @@ uut: WB_bus_adapter_streaming_sg generic map ( g_adr_width_A => 32,
B_STALL_i => src_i.stall,
B_DAT_i => (others => '0'));
nRst_conv <= nRst_i AND NOT conv_reset;
timeout : process(clk_i)
timeout : process(clk_i)
begin
if rising_edge(clk_i) then
--Counter: Timeout
......@@ -354,168 +312,145 @@ end process;
main_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
--==========================================================================
-- SYNC RESET
--==========================================================================
if (nRST_i = '0') then
ETH_TX <= INIT_ETH_HDR (my_mac_i);
IPV4_TX <= INIT_IPV4_HDR(my_ip_i);
UDP_TX <= INIT_UDP_HDR (my_port_i);
state_mux <= NONE;
ld_hdr <= '0';
ld_p_chk_vals <= '0';
sh_chk_en <= '0';
calc_chk_en <= '0';
s_src_padding_o <= (cyc => '1',
stb => '0',
adr => (others => '0'),
sel => (others => '1'),
we => '1',
dat => x"9AD1");
s_src_hdr_o.cyc <= '1';
s_src_hdr_o.stb <= '0';
s_src_hdr_o.adr <= (others => '0');
s_src_hdr_o.we <= '1';
s_src_hdr_o.sel <= (others => '1');
TX_HDR_slv <= (others => '0');
s_ETH_end <= c_ETH_HLEN -2;
conv_reset<= '0';
else
if rising_edge(clk_i) then
--==========================================================================
-- SYNC RESET
--==========================================================================
if (nRST_i = '0') then
ETH_TX <= INIT_ETH_HDR (my_mac_i);
IPV4_TX <= INIT_IPV4_HDR(my_ip_i);
UDP_TX <= INIT_UDP_HDR (my_port_i);
TX_HDR_slv <= (others => '0');
state_mux <= NONE;
ld_hdr <= '0';
ld_p_chk_vals <= '0';
sh_chk_en <= '0';
calc_chk_en <= '0';
s_src_hdr_o.cyc <= '1';
s_src_hdr_o.stb <= '0';
s_src_hdr_o.adr <= (others => '0');
s_src_hdr_o.we <= '1';
s_src_hdr_o.sel <= (others => '1');
s_ETH_end <= c_ETH_HLEN -2;
conv_reset <= '0';
s_src_padding_o <= (cyc => '1',
stb => '0',
adr => (others => '0'),
sel => (others => '1'),
we => '1',
dat => x"9AD1");
else
if(a_timeout = "0") then
ld_hdr <= '0';
ld_p_chk_vals <= '0';
sh_chk_en <= '0';
calc_chk_en <= '0';
conv_reset <= '0';
if(a_timeout = "0") then
ld_hdr <= '0';
case state is
when IDLE => state_mux <= NONE;
if(valid_i = '1' AND silent_i = '0') then
ETH_TX <= INIT_ETH_HDR (my_mac_i); --init all header blocks
IPV4_TX <= INIT_IPV4_HDR(my_ip_i);
UDP_TX <= INIT_UDP_HDR (my_port_i);
ETH_TX.DST <= reply_MAC_i;
IPV4_TX.DST <= reply_IP_i;
IPV4_TX.TOL <= TOL_i;
UDP_TX.MLEN <= payload_len_i;
UDP_TX.DST_PORT <= reply_PORT_i;
ld_p_chk_vals <= '1';
state <= CALC_CHKSUM;
end if;
ld_p_chk_vals <= '0';
sh_chk_en <= '0';
calc_chk_en <= '0';
conv_reset <= '0';
case state is
when IDLE => state_mux <= NONE;
if(valid_i = '1' AND silent_i = '0') then
ETH_TX <= INIT_ETH_HDR (my_mac_i);
IPV4_TX <= INIT_IPV4_HDR(my_ip_i);
UDP_TX <= INIT_UDP_HDR (my_port_i);
ETH_TX.DST <= reply_MAC_i;
IPV4_TX.DST <= reply_IP_i;
IPV4_TX.TOL <= TOL_i;
UDP_TX.MLEN <= payload_len_i;
UDP_TX.DST_PORT <= reply_PORT_i;
ld_p_chk_vals <= '1';
state <= CALC_CHKSUM;
end if;
when CALC_CHKSUM => if(chksum_empty = '0') then
sh_chk_en <= '1';
calc_chk_en <= '1';
else
if(chksum_done = '1') then
IPV4_TX.SUM <= IP_chk_sum;
ld_hdr <= '1';
state <= WAIT_SEND_REQ;
end if;
end if;
when WAIT_SEND_REQ =>
if(silent_i = '1') then
state <= IDLE;
elsif(wb_slave_i.CYC = '1') then
state <= PREP_ETH;
state_mux <= HEADER;
end if;
when PREP_ETH =>
TX_HDR_slv(TX_HDR_slv'left downto TX_HDR_slv'length-c_ETH_HLEN*8) <= to_std_logic_vector(ETH_TX);
s_ETH_end <= c_ETH_HLEN -2;
ld_hdr <= '1';
state <= ETH;
when ETH =>
s_src_hdr_o.stb <= '1';
if(byte_count = s_ETH_end and src_i.stall = '0') then
TX_HDR_slv <= to_std_logic_vector(IPV4_TX);
ld_hdr <= '1';
state <= IPV4;
s_src_hdr_o.stb <= '0';
end if;
when IPV4 => s_src_hdr_o.stb <= '1';
if((byte_count = (s_ETH_end + c_IPV4_HLEN)) and src_i.stall = '0') then
TX_HDR_slv(TX_HDR_slv'left downto TX_HDR_slv'length-c_UDP_HLEN*8) <= to_std_logic_vector(UDP_TX);
ld_hdr <= '1';
state <= UDP;
s_src_hdr_o.stb <= '0';
end if;
when UDP => s_src_hdr_o.stb <= '1';
if(byte_count = (s_ETH_end + c_IPV4_HLEN + c_UDP_HLEN) and src_i.stall = '0') then
state <= HDR_SEND;
s_src_hdr_o.stb <= '0';
end if;
when HDR_SEND => state_mux <= PAYLOAD;
state <= PAYLOAD_SEND;
when CALC_CHKSUM => if(chksum_empty = '0') then --calculate ip checksum
sh_chk_en <= '1';
calc_chk_en <= '1';
else
if(chksum_done = '1') then
IPV4_TX.SUM <= IP_chk_sum;
ld_hdr <= '1';
state <= WAIT_SEND_REQ;
end if;
end if;
when WAIT_SEND_REQ => if(silent_i = '1') then
state <= IDLE;
elsif(wb_slave_i.CYC = '1') then
state <= PREP_ETH;
state_mux <= HEADER;
end if;
when PAYLOAD_SEND => if( s_src_payload_o.cyc = '0') then
if(byte_count < c_ETH_FRAME_MIN_END) then
state <= PADDING;
state_mux <= PADDING;
elsif(byte_count /= to_integer(unsigned(IPV4_TX.TOL)+14)) then
state <= ERROR;
else
state <= WAIT_IFGAP;
state_mux <= NONE;
end if;
end if;
when PADDING => s_src_padding_o.stb <= '1';
if((byte_count >= c_ETH_FRAME_MIN_END) and src_i.stall = '0') then
s_src_padding_o.stb <= '0';
state <= WAIT_IFGAP;
state_mux <= NONE;
end if;
when WAIT_IFGAP => --ensure interframe gap
--if(counter_ouput < 10) then
-- counter_ouput <= counter_ouput +1;
--else
state <= IDLE;
--end if;
when ERROR => state <= IDLE;
report ("TX: ERROR - Wrong packet size. Expected " & integer'image(byte_count) & " found " & integer'image(to_integer(unsigned(IPV4_TX.TOL)+14))) severity error;
when others => state <= IDLE;
when PREP_ETH => TX_HDR_slv(TX_HDR_slv'left downto TX_HDR_slv'length-c_ETH_HLEN*8) <= to_std_logic_vector(ETH_TX);
s_ETH_end <= c_ETH_HLEN -2;
ld_hdr <= '1';
state <= ETH;
when ETH => s_src_hdr_o.stb <= '1';
if(byte_count = s_ETH_end and src_i.stall = '0') then
TX_HDR_slv <= to_std_logic_vector(IPV4_TX);
ld_hdr <= '1';
state <= IPV4;
s_src_hdr_o.stb <= '0';
end if;
when IPV4 => s_src_hdr_o.stb <= '1';
if((byte_count = (s_ETH_end + c_IPV4_HLEN)) and src_i.stall = '0') then
TX_HDR_slv(TX_HDR_slv'left downto TX_HDR_slv'length-c_UDP_HLEN*8) <= to_std_logic_vector(UDP_TX);
ld_hdr <= '1';
state <= UDP;
s_src_hdr_o.stb <= '0';
end if;
when UDP => s_src_hdr_o.stb <= '1';
if(byte_count = (s_ETH_end + c_IPV4_HLEN + c_UDP_HLEN) and src_i.stall = '0') then
state <= HDR_SEND;
s_src_hdr_o.stb <= '0';
end if;
when HDR_SEND => state_mux <= PAYLOAD;
state <= PAYLOAD_SEND;
when PAYLOAD_SEND => if( s_src_payload_o.cyc = '0') then
if(byte_count < c_ETH_FRAME_MIN_END) then
state <= PADDING;
state_mux <= PADDING;
elsif(byte_count /= to_integer(unsigned(IPV4_TX.TOL)+14)) then
state <= ERRORS;
else
state <= WAIT_IFGAP;
state_mux <= NONE;
end if;
end if;
end case;
else
state <= IDLE;
state_mux <= NONE;
conv_reset <= '1';
end if;
when PADDING => s_src_padding_o.stb <= '1';
if((byte_count >= c_ETH_FRAME_MIN_END) and src_i.stall = '0') then
s_src_padding_o.stb <= '0';
state <= WAIT_IFGAP;
state_mux <= NONE;
end if;
when WAIT_IFGAP => state <= IDLE;
when ERRORS => state <= IDLE;
report ("TX: ERRORS - Wrong packet size. Expected " & integer'image(byte_count) & " found " & integer'image(to_integer(unsigned(IPV4_TX.TOL)+14))) severity error;
when others => state <= IDLE;
end case;
else
state <= IDLE;
state_mux <= NONE;
conv_reset <= '1';
end if;
end if;
end if;
end if;
end process;
......
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