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Commit 7bf12085 authored by Wesley W. Terpstra's avatar Wesley W. Terpstra
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eb2: integrate new FSM with top components

parent 0bcf6830
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hdl/eb_slave_core/Manifest.py
+ 16
− 4
View file @ 7bf12085
files = [ files = [
"eb_rx_fsm.vhd", "eb_internals_pkg.vhd",
"eb_cfg_fifo.vhd",
"eb_fifo.vhd", "eb_fifo.vhd",
"eb_cfg_fifo.vhd",
"eb_pass_fifo.vhd", "eb_pass_fifo.vhd",
"eb_tag_fifo.vhd", "eb_tag_fifo.vhd",
"eb_wbm_fifo.vhd", "eb_wbm_fifo.vhd",
"eb_internals_pkg.vhd", "eb_rx_fsm.vhd",
"eb_tx_mux.vhd",
"eb_slave.vhd",
# files below this point need refactoring:
"eb_hdr_pkg.vhd", "eb_hdr_pkg.vhd",
"eb_slave.vhd" "eb_usb_slave_core.vhd",
"eb_slave_core.vhd",
"etherbone_pkg.vhd",
"eb_tx_ctrl.vhd",
"eb_rx_ctrl.vhd",
"WB_bus_adapter_streaming_sg.vhd",
"vhdl_2008_workaround_pkg.vhd",
"eb_checksum.vhd",
"piso_flag.vhd",
"sipo_flag.vhd"
] ]
hdl/eb_slave_core/eb_cfg_fifo.vhd
+ 9
− 1
View file @ 7bf12085
...@@ -44,7 +44,11 @@ entity eb_cfg_fifo is ...@@ -44,7 +44,11 @@ entity eb_cfg_fifo is
mux_pop_i : in std_logic; mux_pop_i : in std_logic;
mux_dat_o : out std_logic_vector(31 downto 0); mux_dat_o : out std_logic_vector(31 downto 0);
mux_empty_o : out std_logic); mux_empty_o : out std_logic;
my_mac_o : out std_logic_vector(47 downto 0);
my_ip_o : out std_logic_vector(31 downto 0);
my_port_o : out std_logic_vector(15 downto 0));
end eb_cfg_fifo; end eb_cfg_fifo;
architecture rtl of eb_cfg_fifo is architecture rtl of eb_cfg_fifo is
...@@ -169,4 +173,8 @@ begin ...@@ -169,4 +173,8 @@ begin
r_ip when "110", r_ip when "110",
c_pad & r_port when others; c_pad & r_port when others;
my_mac_o <= r_mac;
my_ip_o <= r_ip;
my_port_o <= r_port;
end rtl; end rtl;
hdl/eb_slave_core/eb_config.vhd deleted 100644 → 0
+ 0
− 189
View file @ 0bcf6830
--! @file EB_config.vhd
--! @brief EtherBone config space memory
--!
--! Copyright (C) 2011-2012 GSI Helmholtz Centre for Heavy Ion Research GmbH
--!
--! Important details about its implementation
--! should go in these comments.
--!
--! @author Mathias Kreider <m.kreider@gsi.de>
--!
--! @bug No know bugs.
--!
--------------------------------------------------------------------------------
--! This library is free software; you can redistribute it and/or
--! modify it under the terms of the GNU Lesser General Public
--! License as published by the Free Software Foundation; either
--! version 3 of the License, or (at your option) any later version.
--!
--! This library is distributed in the hope that it will be useful,
--! but WITHOUT ANY WARRANTY; without even the implied warranty of
--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--! Lesser General Public License for more details.
--!
--! You should have received a copy of the GNU Lesser General Public
--! License along with this library. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
entity eb_config is
generic(
g_sdb_address : std_logic_vector(63 downto 0));
port(
clk_i : in std_logic; --clock
nRST_i : in std_logic;
status_i : in std_logic;
status_en : in std_logic;
status_clr : in std_logic;
my_mac_o : out std_logic_vector(6*8-1 downto 0);
my_ip_o : out std_logic_vector(4*8-1 downto 0);
my_port_o : out std_logic_vector(2*8-1 downto 0);
local_slave_o : out t_wishbone_slave_out;
local_slave_i : in t_wishbone_slave_in; --! local Wishbone master lines
eb_slave_o : out t_wishbone_slave_out; --! EB Wishbone slave lines
eb_slave_i : in t_wishbone_slave_in
);
end eb_config;
architecture behavioral of eb_config is
subtype dword is std_logic_vector(31 downto 0);
type mem is array (0 to 2) of dword;
signal my_mem : mem;
signal eb_adr : natural;
signal local_adr : natural;
signal local_write_reg : std_logic_vector(31 downto 0);
signal status_reg : std_logic_vector(63 downto 0);
signal p_auto_cfg : std_logic_vector(63 downto 0);
signal my_mac : std_logic_vector(6*8-1 downto 0);
signal my_ip : std_logic_vector(4*8-1 downto 0);
signal my_port : std_logic_vector(2*8-1 downto 0);
constant c_my_default_mac : std_logic_vector(6*8-1 downto 0) := x"D15EA5EDBEEF";
constant c_my_default_ip : std_logic_vector(4*8-1 downto 0) := x"C0A80064";
constant c_my_default_port : std_logic_vector(2*8-1 downto 0) := x"EBD0";
begin
eb_adr <= to_integer(unsigned(eb_slave_i.ADR(7 downto 2)) & "00");
local_adr <= to_integer(unsigned(local_slave_i.ADR(7 downto 2)) & "00");
my_mac_o <= my_mac;
my_ip_o <= my_ip;
my_port_o <= my_port;
local_slave_o.STALL <= eb_slave_i.CYC;
local_slave_o.INT <= '0';
local_slave_o.RTY <= '0';
eb_if : process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(nRSt_i = '0') then
eb_slave_o <= (
ACK => '0',
ERR => '0',
RTY => '0',
STALL => '0',
INT => '0',
DAT => (others => '0'));
local_slave_o.ACK <= '0';
local_slave_o.ERR <= '0';
local_slave_o.DAT <= (others => '0');
my_ip <= c_my_default_ip;
my_mac <= c_my_default_mac;
my_port <= c_my_default_port;
p_auto_cfg <= g_sdb_address;
else
--EB Side
eb_slave_o.ACK <= eb_slave_i.CYC and eb_slave_i.STB;
if(eb_slave_i.STB = '1' and eb_slave_i.CYC = '1') then
if(eb_slave_i.WE = '1') then
case eb_adr is
when 0 => null;
when 16 => my_mac(47 downto 16) <= eb_slave_i.DAT(31 downto 0);
when 20 => my_mac(15 downto 0) <= eb_slave_i.DAT(31 downto 16);
when 24 => my_ip <= eb_slave_i.DAT;
when 28 => my_port <= eb_slave_i.DAT(31 downto 16);
when others => null;
end case;
else
case eb_adr is
when 0 => eb_slave_o.DAT <= status_reg(63 downto 32);
when 4 => eb_slave_o.DAT <= status_reg(31 downto 0);
when 8 => eb_slave_o.DAT <= p_auto_cfg(63 downto 32);
when 12 => eb_slave_o.DAT <= p_auto_cfg(31 downto 0);
when 16 => eb_slave_o.DAT <= my_mac(47 downto 16);
when 20 => eb_slave_o.DAT <= (my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16)));
when 24 => eb_slave_o.DAT <= my_ip;
when 28 => eb_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16));
when others => eb_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
end if;
--Local Side
local_slave_o.ACK <= local_slave_i.STB and local_slave_i.CYC and not eb_slave_i.CYC;
if(local_slave_i.STB = '1' and local_slave_i.CYC = '1' and eb_slave_i.CYC = '0') then
if(local_slave_i.WE = '1') then
case local_adr is
when 8 => p_auto_cfg(63 downto 32) <= local_slave_i.DAT;
when 12 => p_auto_cfg(31 downto 0) <= local_slave_i.DAT;
when 16 => my_mac(47 downto 16) <= local_slave_i.DAT(31 downto 0);
when 20 => my_mac(15 downto 0) <= local_slave_i.DAT(31 downto 16);
when 24 => my_ip <= local_slave_i.DAT;
when 28 => my_port <= local_slave_i.DAT(31 downto 16);
when others => null;
end case;
else
case local_adr is
when 0 => local_slave_o.DAT <= status_reg(63 downto 32);
when 4 => local_slave_o.DAT <= status_reg(31 downto 0);
when 8 => local_slave_o.DAT <= p_auto_cfg(63 downto 32);
when 12 => local_slave_o.DAT <= p_auto_cfg(31 downto 0);
when 16 => local_slave_o.DAT <= my_mac(47 downto 16);
when 20 => local_slave_o.DAT <= my_mac(15 downto 0) & std_logic_vector(to_unsigned(0, 16));
when 24 => local_slave_o.DAT <= my_ip;
when 28 => local_slave_o.DAT <= my_port & std_logic_vector(to_unsigned(0, 16));
when others => local_slave_o.DAT <= status_reg(63 downto 32);
end case;
end if;
end if;
end if;
end if;
end process;
status_reg_sh : process(clk_i)
begin
if (clk_i'event and clk_i = '1') then
if(nRSt_i = '0') then
status_reg <= (others => '0');
else
if(status_clr = '1') then
--status_reg <= (others => '0');
elsif(status_en = '1') then
status_reg <= status_reg(status_reg'left-1 downto 0) & status_i;
end if;
end if;
end if;
end process;
end behavioral;
hdl/eb_slave_core/eb_internals_pkg.vhd
+ 27
− 1
View file @ 7bf12085
...@@ -16,6 +16,28 @@ package eb_internals_pkg is ...@@ -16,6 +16,28 @@ package eb_internals_pkg is
constant c_tag_cfg_req : t_tag := "01"; constant c_tag_cfg_req : t_tag := "01";
constant c_tag_pass_on : t_tag := "10"; constant c_tag_pass_on : t_tag := "10";
component eb_slave is
generic(
g_sdb_address : t_wishbone_address);
port(
clk_i : in std_logic; --! System Clk
nRst_i : in std_logic; --! active low sync reset
EB_RX_i : in t_wishbone_slave_in; --! Streaming wishbone(record) sink from RX transport protocol block
EB_RX_o : out t_wishbone_slave_out; --! Streaming WB sink flow control to RX transport protocol block
EB_TX_i : in t_wishbone_master_in; --! Streaming WB src flow control from TX transport protocol block
EB_TX_o : out t_wishbone_master_out; --! Streaming WB src to TX transport protocol block
WB_config_i : in t_wishbone_slave_in; --! WB V4 interface to WB interconnect/device(s)
WB_config_o : out t_wishbone_slave_out; --! WB V4 interface to WB interconnect/device(s)
WB_master_i : in t_wishbone_master_in; --! WB V4 interface to WB interconnect/device(s)
WB_master_o : out t_wishbone_master_out; --! WB V4 interface to WB interconnect/device(s)
my_mac_o : out std_logic_vector(47 downto 0);
my_ip_o : out std_logic_vector(31 downto 0);
my_port_o : out std_logic_vector(15 downto 0));
end component;
component eb_rx_fsm is component eb_rx_fsm is
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
...@@ -130,7 +152,11 @@ package eb_internals_pkg is ...@@ -130,7 +152,11 @@ package eb_internals_pkg is
mux_pop_i : in std_logic; mux_pop_i : in std_logic;
mux_dat_o : out std_logic_vector(31 downto 0); mux_dat_o : out std_logic_vector(31 downto 0);
mux_empty_o : out std_logic); mux_empty_o : out std_logic;
my_mac_o : out std_logic_vector(47 downto 0);
my_ip_o : out std_logic_vector(31 downto 0);
my_port_o : out std_logic_vector(15 downto 0));
end component; end component;
component eb_wbm_fifo is component eb_wbm_fifo is
......
hdl/eb_slave_core/eb_main_fsm.vhd deleted 100644 → 0
+ 0
− 923
View file @ 0bcf6830
This diff is collapsed.
hdl/eb_slave_core/eb_slave.vhd
+ 9
− 2
View file @ 7bf12085
...@@ -42,7 +42,11 @@ entity eb_slave is ...@@ -42,7 +42,11 @@ entity eb_slave is
WB_config_i : in t_wishbone_slave_in; --! WB V4 interface to WB interconnect/device(s) WB_config_i : in t_wishbone_slave_in; --! WB V4 interface to WB interconnect/device(s)
WB_config_o : out t_wishbone_slave_out; --! WB V4 interface to WB interconnect/device(s) WB_config_o : out t_wishbone_slave_out; --! WB V4 interface to WB interconnect/device(s)
WB_master_i : in t_wishbone_master_in; --! WB V4 interface to WB interconnect/device(s) WB_master_i : in t_wishbone_master_in; --! WB V4 interface to WB interconnect/device(s)
WB_master_o : out t_wishbone_master_out); --! WB V4 interface to WB interconnect/device(s) WB_master_o : out t_wishbone_master_out; --! WB V4 interface to WB interconnect/device(s)
my_mac_o : out std_logic_vector(47 downto 0);
my_ip_o : out std_logic_vector(31 downto 0);
my_port_o : out std_logic_vector(15 downto 0));
end eb_slave; end eb_slave;
architecture rtl of eb_slave is architecture rtl of eb_slave is
...@@ -169,7 +173,10 @@ begin ...@@ -169,7 +173,10 @@ begin
fsm_full_o => cfg_fsm_full, fsm_full_o => cfg_fsm_full,
mux_pop_i => mux_cfg_pop, mux_pop_i => mux_cfg_pop,
mux_dat_o => cfg_mux_dat, mux_dat_o => cfg_mux_dat,
mux_empty_o => cfg_mux_empty); mux_empty_o => cfg_mux_empty,
my_mac_o => my_mac_o,
my_ip_o => my_ip_o,
my_port_o => my_port_o);
WB_master_o.cyc <= fsm_wbm_wb.cyc; WB_master_o.cyc <= fsm_wbm_wb.cyc;
wbm : eb_wbm_fifo wbm : eb_wbm_fifo
......
hdl/eb_slave_core/eb_slave_core.vhd
+ 12
− 40
View file @ 7bf12085
...@@ -36,6 +36,7 @@ use work.etherbone_pkg.all; ...@@ -36,6 +36,7 @@ use work.etherbone_pkg.all;
use work.eb_hdr_pkg.all; use work.eb_hdr_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.eb_internals_pkg.all;
entity eb_slave_core is entity eb_slave_core is
...@@ -70,8 +71,6 @@ end eb_slave_core; ...@@ -70,8 +71,6 @@ end eb_slave_core;
architecture behavioral of eb_slave_core is architecture behavioral of eb_slave_core is
signal s_status_en : std_logic;
signal s_status_clr : std_logic;
signal DEBUG_WB_master_o : t_wishbone_master_out; signal DEBUG_WB_master_o : t_wishbone_master_out;
signal WB_master_i : t_wishbone_master_in; signal WB_master_i : t_wishbone_master_in;
...@@ -187,7 +186,7 @@ begin ...@@ -187,7 +186,7 @@ begin
my_ip_i => CFG_MY_IP, my_ip_i => CFG_MY_IP,
my_port_i => CFG_MY_PORT, my_port_i => CFG_MY_PORT,
my_vlan_i => (others => '0'), my_vlan_i => (others => '0'),
silent_i => EB_2_TXCTRL_silent, silent_i => EB_TX_o.cyc,
valid_i => RXCTRL_2_TXCTRL_valid valid_i => RXCTRL_2_TXCTRL_valid
); );
...@@ -216,7 +215,9 @@ begin ...@@ -216,7 +215,9 @@ begin
EB : eb_main_fsm EB : eb_slave
generic map(
g_sdb_address => g_sdb_address(31 downto 0))
port map( port map(
--general --general
clk_i => clk_i, clk_i => clk_i,
...@@ -225,45 +226,16 @@ begin ...@@ -225,45 +226,16 @@ begin
--Eth MAC WB Streaming signals --Eth MAC WB Streaming signals
EB_RX_i => RXCTRL_2_EB_wb_slave, EB_RX_i => RXCTRL_2_EB_wb_slave,
EB_RX_o => EB_2_RXCTRL_wb_slave, EB_RX_o => EB_2_RXCTRL_wb_slave,
EB_TX_i => TXCTRL_2_EB_wb_master,
EB_TX_o => EB_2_TXCTRL_wb_master,
EB_TX_i => TXCTRL_2_EB_wb_master, WB_config_i => EXT_2_CFG_slave,
EB_TX_o => EB_2_TXCTRL_wb_master, WB_config_o => CFG_2_EXT_slave,
TX_silent_o => EB_2_TXCTRL_silent,
byte_count_rx_i => RXCTRL_2_CORE_LEN,
config_master_i => CFG_2_eb_slave,
config_master_o => eb_2_CFG_slave,
--WB IC signals
WB_master_i => WB_master_i, WB_master_i => WB_master_i,
WB_master_o => DEBUG_WB_master_o WB_master_o => DEBUG_WB_master_o,
);
s_status_en <= WB_master_i.ACK or WB_master_i.ERR;
s_status_clr <= not DEBUG_WB_master_o.CYC;
cfg_space : eb_config
generic map(
g_sdb_address => g_sdb_address)
port map(
--general
clk_i => clk_i,
nRst_i => nRst_i,
status_i => WB_master_i.ERR,
status_en => s_status_en,
status_clr => s_status_clr,
my_mac_o => CFG_MY_MAC, my_mac_o => CFG_MY_MAC,
my_ip_o => CFG_MY_IP, my_ip_o => CFG_MY_IP,
my_port_o => CFG_MY_PORT, my_port_o => CFG_MY_PORT);
local_slave_o => CFG_2_EXT_slave,
local_slave_i => EXT_2_CFG_slave,
eb_slave_o => CFG_2_eb_slave,
eb_slave_i => eb_2_CFG_slave
);
end behavioral; end behavioral;
hdl/eb_slave_core/eb_usb_slave_core.vhd
+ 10
− 37
View file @ 7bf12085
...@@ -36,7 +36,7 @@ use work.etherbone_pkg.all; ...@@ -36,7 +36,7 @@ use work.etherbone_pkg.all;
use work.eb_hdr_pkg.all; use work.eb_hdr_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wr_fabric_pkg.all; use work.wr_fabric_pkg.all;
use work.eb_internals_pkg.all;
entity eb_usb_slave_core is entity eb_usb_slave_core is
generic(g_sdb_address : std_logic_vector(63 downto 0) := x"01234567ABCDEF00"); generic(g_sdb_address : std_logic_vector(63 downto 0) := x"01234567ABCDEF00");
...@@ -203,7 +203,9 @@ scatter: WB_bus_adapter_streaming_sg generic map (g_adr_width_A => 32, ...@@ -203,7 +203,9 @@ scatter: WB_bus_adapter_streaming_sg generic map (g_adr_width_A => 32,
src_o.sel <= "000" & B_SEL_o; src_o.sel <= "000" & B_SEL_o;
EB : eb_main_fsm EB : eb_slave
generic map(
g_sdb_address => g_sdb_address(31 downto 0))
port map( port map(
--general --general
clk_i => clk_i, clk_i => clk_i,
...@@ -212,45 +214,16 @@ scatter: WB_bus_adapter_streaming_sg generic map (g_adr_width_A => 32, ...@@ -212,45 +214,16 @@ scatter: WB_bus_adapter_streaming_sg generic map (g_adr_width_A => 32,
--Eth MAC WB Streaming signals --Eth MAC WB Streaming signals
EB_RX_i => s_gather_2_eb_main_fsm, EB_RX_i => s_gather_2_eb_main_fsm,
EB_RX_o => s_eb_main_fsm_2_gather, EB_RX_o => s_eb_main_fsm_2_gather,
EB_TX_i => s_scatter_2_eb_main_fsm, EB_TX_i => s_scatter_2_eb_main_fsm,
EB_TX_o => s_eb_main_fsm_2_scatter, EB_TX_o => s_eb_main_fsm_2_scatter,
TX_silent_o => open,
byte_count_rx_i => (others => '0'), WB_config_i => EXT_2_CFG_slave,
WB_config_o => CFG_2_EXT_slave,
config_master_i => CFG_2_eb_slave,
config_master_o => eb_2_CFG_slave,
--WB IC signals
WB_master_i => WB_master_i, WB_master_i => WB_master_i,
WB_master_o => DEBUG_WB_master_o WB_master_o => DEBUG_WB_master_o,
);
s_status_en <= WB_master_i.ACK or WB_master_i.ERR;
s_status_clr <= not DEBUG_WB_master_o.CYC;
cfg_space : eb_config
generic map(
g_sdb_address => g_sdb_address)
port map(
--general
clk_i => clk_i,
nRst_i => nRst_i,
status_i => WB_master_i.ERR,
status_en => s_status_en,
status_clr => s_status_clr,
my_mac_o => open, my_mac_o => open,
my_ip_o => open, my_ip_o => open,
my_port_o => open, my_port_o => open);
local_slave_o => CFG_2_EXT_slave,
local_slave_i => EXT_2_CFG_slave,
eb_slave_o => CFG_2_eb_slave,
eb_slave_i => eb_2_CFG_slave
);
end behavioral; end behavioral;
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