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EtherBone Core
Commits
615c01a1
Commit
615c01a1
authored
13 years ago
by
Wesley W. Terpstra
Browse files
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Align accesses to work with new API.
Prepare to test also sub-word accesses.
parent
c6aed681
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1
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1 changed file
api/test/loopback.cpp
+22
-10
22 additions, 10 deletions
api/test/loopback.cpp
with
22 additions
and
10 deletions
api/test/loopback.cpp
+
22
−
10
View file @
615c01a1
...
@@ -57,16 +57,21 @@ enum RecordType { READ_BUS, READ_CFG, WRITE_BUS, WRITE_CFG };
...
@@ -57,16 +57,21 @@ enum RecordType { READ_BUS, READ_CFG, WRITE_BUS, WRITE_CFG };
struct
Record
{
struct
Record
{
address_t
address
;
address_t
address
;
data_t
data
;
data_t
data
;
width_t
width
;
bool
error
;
bool
error
;
RecordType
type
;
RecordType
type
;
Record
(
width_t
width
);
Record
(
width_t
width
);
};
};
Record
::
Record
(
width_t
width
)
{
Record
::
Record
(
width_t
width
_
)
{
static
address_t
prev
=
0
;
static
address_t
prev
=
0
;
long
seed
=
rand
();
long
seed
=
rand
();
width_t
addrw
=
width_
>>
4
;
width_t
dataw
=
width_
&
EB_DATAX
;
width
=
(
addrw
<<
4
)
|
dataw
;
address
=
rand
();
address
=
rand
();
address
+=
address
*
RAND_MAX
;
address
+=
address
*
RAND_MAX
;
address
+=
rand
();
address
+=
rand
();
...
@@ -100,17 +105,21 @@ Record::Record(width_t width) {
...
@@ -100,17 +105,21 @@ Record::Record(width_t width) {
error
=
0
;
error
=
0
;
}
else
{
}
else
{
/* Trim the request to fit the addr/data widths */
/* Trim the request to fit the addr/data widths */
data
&=
(
data_t
)(
~
0
)
>>
((
sizeof
(
data
)
-
(
width
&
EB_DATAX
)
)
*
8
);
data
&=
(
data_t
)(
~
0
)
>>
((
sizeof
(
data
)
-
dataw
)
*
8
);
address
&=
(
address_t
)(
~
0
)
>>
((
sizeof
(
address
)
-
(
width
>>
4
)
)
*
8
);
address
&=
(
address_t
)(
~
0
)
>>
((
sizeof
(
address
)
-
addrw
)
*
8
);
error
=
(
address
&
3
)
==
1
;
error
=
(
address
&
3
)
==
1
;
}
}
/* Introduce a high chance for FIFO/seq access */
/* Introduce a high chance for FIFO/seq access */
if
((
seed
&
3
)
!=
3
&&
(
type
==
WRITE_BUS
||
type
==
WRITE_CFG
))
{
if
((
seed
&
3
)
!=
3
)
{
address
=
prev
&
0x7FFF
;
if
(
type
==
WRITE_BUS
)
address
=
prev
;
if
(
type
==
WRITE_CFG
)
address
=
prev
&
0x7FFF
;
}
else
{
}
else
{
prev
=
address
;
prev
=
address
;
}
}
/* Align the access */
address
&=
~
(
address_t
)(
dataw
-
1
);
}
}
list
<
Record
>
expect
;
list
<
Record
>
expect
;
...
@@ -129,6 +138,7 @@ status_t Echo::read (address_t address, width_t width, data_t* data) {
...
@@ -129,6 +138,7 @@ status_t Echo::read (address_t address, width_t width, data_t* data) {
expect
.
pop_front
();
expect
.
pop_front
();
/* Confirm it's as we expect */
/* Confirm it's as we expect */
if
(
r
.
width
!=
width
)
die
(
"wrong width recvd"
,
EB_FAIL
);
if
(
r
.
type
!=
READ_BUS
)
die
(
"wrong op recvd"
,
EB_FAIL
);
if
(
r
.
type
!=
READ_BUS
)
die
(
"wrong op recvd"
,
EB_FAIL
);
if
(
r
.
address
!=
address
)
die
(
"wrong addr recvd"
,
EB_FAIL
);
if
(
r
.
address
!=
address
)
die
(
"wrong addr recvd"
,
EB_FAIL
);
...
@@ -149,6 +159,7 @@ status_t Echo::write(address_t address, width_t width, data_t data) {
...
@@ -149,6 +159,7 @@ status_t Echo::write(address_t address, width_t width, data_t data) {
expect
.
pop_front
();
expect
.
pop_front
();
/* Confirm it's as we expect */
/* Confirm it's as we expect */
if
(
r
.
width
!=
width
)
die
(
"wrong width recvd"
,
EB_FAIL
);
if
(
r
.
type
!=
WRITE_BUS
)
die
(
"wrong op recvd"
,
EB_FAIL
);
if
(
r
.
type
!=
WRITE_BUS
)
die
(
"wrong op recvd"
,
EB_FAIL
);
if
(
r
.
address
!=
address
)
die
(
"wrong addr recvd"
,
EB_FAIL
);
if
(
r
.
address
!=
address
)
die
(
"wrong addr recvd"
,
EB_FAIL
);
if
(
r
.
data
!=
data
)
die
(
"wrong data recvd"
,
EB_FAIL
);
if
(
r
.
data
!=
data
)
die
(
"wrong data recvd"
,
EB_FAIL
);
...
@@ -218,11 +229,12 @@ void TestCycle::launch(Device device, int length, int* success_) {
...
@@ -218,11 +229,12 @@ void TestCycle::launch(Device device, int length, int* success_) {
for
(
int
op
=
0
;
op
<
length
;
++
op
)
{
for
(
int
op
=
0
;
op
<
length
;
++
op
)
{
Record
r
(
device
.
width
());
Record
r
(
device
.
width
());
switch
(
r
.
type
)
{
switch
(
r
.
type
)
{
case
READ_BUS
:
cycle
.
read
(
r
.
address
,
EB_DATAX
,
0
);
break
;
case
READ_BUS
:
cycle
.
read
(
r
.
address
,
r
.
width
,
0
);
break
;
case
READ_CFG
:
cycle
.
read_config
(
r
.
address
,
EB_DATAX
,
0
);
break
;
case
READ_CFG
:
cycle
.
read_config
(
r
.
address
,
r
.
width
,
0
);
break
;
case
WRITE_BUS
:
cycle
.
write
(
r
.
address
,
EB_DATAX
,
r
.
data
);
break
;
case
WRITE_BUS
:
cycle
.
write
(
r
.
address
,
r
.
width
,
r
.
data
);
break
;
case
WRITE_CFG
:
cycle
.
write_config
(
r
.
address
,
EB_DATAX
,
r
.
data
);
break
;
case
WRITE_CFG
:
cycle
.
write_config
(
r
.
address
,
r
.
width
,
r
.
data
);
break
;
}
}
records
.
push_back
(
r
);
records
.
push_back
(
r
);
...
@@ -250,7 +262,7 @@ void test_query(Device device, int len, int requests) {
...
@@ -250,7 +262,7 @@ void test_query(Device device, int len, int requests) {
++
serial
;
++
serial
;
#if 0
#if 0
if (serial == 9
1845
) {
if (serial == 9
09
) {
printf("Enabling debug\n");
printf("Enabling debug\n");
loud = true;
loud = true;
}
}
...
...
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